In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design...In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.展开更多
随着集成电路设计复杂度的不断提高,IP核(Intellectual Property Core)作为可复用的电路模块,已成为现代芯片设计的重要组成部分。IP核的正确性、可靠性和性能直接影响到SoC(System on Chip)的整体质量和开发效率。然而,当前IP核评测标...随着集成电路设计复杂度的不断提高,IP核(Intellectual Property Core)作为可复用的电路模块,已成为现代芯片设计的重要组成部分。IP核的正确性、可靠性和性能直接影响到SoC(System on Chip)的整体质量和开发效率。然而,当前IP核评测标准存在不统一、验证不充分等问题,亟需建立一套科学、全面的评测方法。本文通过对IP核设计验证和硅验证方法的深入研究,提出了一套结合设计验证和硅验证的IP核评测标准。该标准涵盖了功能验证、性能验证、面积检查、代码质量检查、可交付信息资料以及硅验证等内容,为IP核的标准化设计、验证与交付提供了明确的指导。研究还分析了现有国际和国内标准的优缺点,并提出了未来研究方向,包括针对特定功能领域(如:人工智能、网络安全等)的细化标准、更高效的验证方法与工具,以及积极参与国际标准的制定与交流。展开更多
基金Project supported by the IC Special Foundation of Shanghai Municipal Commission of Science and Technology (Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information (Grant No.090344)the Shanghai High-Tech Industrialization of New Energy Vehicles (Grant No.09625029),and the Graduate Innovation Foundation of Shanghai University
文摘In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.
文摘随着集成电路设计复杂度的不断提高,IP核(Intellectual Property Core)作为可复用的电路模块,已成为现代芯片设计的重要组成部分。IP核的正确性、可靠性和性能直接影响到SoC(System on Chip)的整体质量和开发效率。然而,当前IP核评测标准存在不统一、验证不充分等问题,亟需建立一套科学、全面的评测方法。本文通过对IP核设计验证和硅验证方法的深入研究,提出了一套结合设计验证和硅验证的IP核评测标准。该标准涵盖了功能验证、性能验证、面积检查、代码质量检查、可交付信息资料以及硅验证等内容,为IP核的标准化设计、验证与交付提供了明确的指导。研究还分析了现有国际和国内标准的优缺点,并提出了未来研究方向,包括针对特定功能领域(如:人工智能、网络安全等)的细化标准、更高效的验证方法与工具,以及积极参与国际标准的制定与交流。
