It is the time to explore the fundamentals of IDDT testing when extensive workhas been done for IDDT testing since it was proposed. This paper precisely defines the concept ofaverage transient current (IDDT) of CMOS d...It is the time to explore the fundamentals of IDDT testing when extensive workhas been done for IDDT testing since it was proposed. This paper precisely defines the concept ofaverage transient current (IDDT) of CMOS digital ICs, and experimentally analyzes the feasibilityof IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests aformula to calculateIDDT by means of counting only logical up-transitions, which enablesIDDT testgeneration at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are withIDDT testability larger than2.5, and likely to beIDDT testable. It is also found that most IDDT testable faults are located nearthe primary inputs of a circuit under test. IDDT test generation does not require fault sensitizationprocedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-atfaults can be detected by using IDDT testing.展开更多
The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classif...The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.展开更多
文摘It is the time to explore the fundamentals of IDDT testing when extensive workhas been done for IDDT testing since it was proposed. This paper precisely defines the concept ofaverage transient current (IDDT) of CMOS digital ICs, and experimentally analyzes the feasibilityof IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests aformula to calculateIDDT by means of counting only logical up-transitions, which enablesIDDT testgeneration at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are withIDDT testability larger than2.5, and likely to beIDDT testable. It is also found that most IDDT testable faults are located nearthe primary inputs of a circuit under test. IDDT test generation does not require fault sensitizationprocedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-atfaults can be detected by using IDDT testing.
基金Supported by the National Natural Science Foun-dation of China (60374008 ,60501022)
文摘The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.
