It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing...It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.展开更多
At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST f...At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.展开更多
Antigen rapid diagnostic tests(Ag-RDTs)have been considered and implemented as an important diagnostic and screening tool to identify SARS-CoV-2 infections in community settings.1 Ag-RDTs are less sensitive,particular...Antigen rapid diagnostic tests(Ag-RDTs)have been considered and implemented as an important diagnostic and screening tool to identify SARS-CoV-2 infections in community settings.1 Ag-RDTs are less sensitive,particularly in asymptomatic populations,compared with laboratorybased viral nucleic acid amplification tests(NAATs)such as reverse transcription polymerase chain reaction(RT-PCR).2 However,taking into account the facts that Ag-RDTs are effective for identifying most contagious individuals,they are faster and less expensive than RT-PCR,as well as that RT-PCR could produce positive results for weeks to months after the infection,2 WHO recommends Ag-RDTs be offered as COVID-19 self-testing for screening purposes in addition to professionally administered testing services regardless of the community transmission level.展开更多
This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression struct...This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.展开更多
Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirement...Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach.展开更多
基金Project supported by the Key Project Science and Technology Cooperation of Fujian Province,China(No.2013I0003)
文摘It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.
基金the National Natural Science Foundation of China under grant Nos.69976002and 69733010.
文摘At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.
基金the State Laboratory of Respiratory Diseases,Guangzhou,China(No.TL22-15)the Municipal Natural Science Foundation of Chongqing,China(No.stc2020jscx-fyzxX0003)Chongqing Biomedical R&D Major Special Project(China)(No.CSTB2022TIAD-STX0013)。
文摘Antigen rapid diagnostic tests(Ag-RDTs)have been considered and implemented as an important diagnostic and screening tool to identify SARS-CoV-2 infections in community settings.1 Ag-RDTs are less sensitive,particularly in asymptomatic populations,compared with laboratorybased viral nucleic acid amplification tests(NAATs)such as reverse transcription polymerase chain reaction(RT-PCR).2 However,taking into account the facts that Ag-RDTs are effective for identifying most contagious individuals,they are faster and less expensive than RT-PCR,as well as that RT-PCR could produce positive results for weeks to months after the infection,2 WHO recommends Ag-RDTs be offered as COVID-19 self-testing for screening purposes in addition to professionally administered testing services regardless of the community transmission level.
基金This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476.
文摘This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.
文摘Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach.
