Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
Si C器件的高功率密度与封装微型化趋势,使得环氧塑封料(EMC)的热-机械性能成为决定器件性能与可靠性的关键因素。在先进的扇出型板级封装(FOPLP)中,这一挑战尤为突出,因为EMC不仅承担绝缘任务,更是结构机械支撑与阻碍散热的主体。为探...Si C器件的高功率密度与封装微型化趋势,使得环氧塑封料(EMC)的热-机械性能成为决定器件性能与可靠性的关键因素。在先进的扇出型板级封装(FOPLP)中,这一挑战尤为突出,因为EMC不仅承担绝缘任务,更是结构机械支撑与阻碍散热的主体。为探究不同EMC对FOPLP热-机械性能的具体影响规律,以2种不同填料体系的商用EMC为研究对象,系统表征了其关键热-机械物性,随后通过热阻与热翘曲实验,揭示了材料差异对封装性能变化的影响。同时,建立了FOPLP结构的热-机械耦合有限元(FEA)仿真模型,进行仿真验证,分析了不同EMC对封装性能的最终影响,并验证了所构建的FEA仿真模型的准确性。研究结果表明Al2O3填充EMC在热阻与热翘曲方面优于SiO2填充EMC,所构建的FEA模型能高精度地预测封装的热机械行为,证实了此实验-仿真综合评估方法的有效性。展开更多
A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer a...A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.展开更多
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
基金supported in part by the National Natural Science Foundation of China(62104220)in part by the National Key Research and Development Program of China(2019YFB2204800).
文摘A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.
