The fabrication of a dynamic threshold-2T0C(DT-2T0C) DRAM cell incorporating a ZnO charge-trap layer in the write transistor has been successfully achieved, addressing the negative hold voltage(V_(HOLD)) issue of conv...The fabrication of a dynamic threshold-2T0C(DT-2T0C) DRAM cell incorporating a ZnO charge-trap layer in the write transistor has been successfully achieved, addressing the negative hold voltage(V_(HOLD)) issue of conventional 2T0C DRAM cells using oxide channel layers. The proposed device facilitates dynamic modulation of turn-on voltage(V_(ON)) through an additional SET operation, allowing V_(ON) to shift above 0 V. The retention time in SET operation was extended to 10^(4) s by optimizing the tunneling layer deposition conditions. The device characterization revealed a significant correlation between V_(ON) and both the WRITE speed and the retention properties of the DT-2T0C, verifying the trade-off between WRITE time and retention time. A long retention time over 1000 s was achieved, even under VHOLD of 0 V.展开更多
基金supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (RS-2024-00334190)。
文摘The fabrication of a dynamic threshold-2T0C(DT-2T0C) DRAM cell incorporating a ZnO charge-trap layer in the write transistor has been successfully achieved, addressing the negative hold voltage(V_(HOLD)) issue of conventional 2T0C DRAM cells using oxide channel layers. The proposed device facilitates dynamic modulation of turn-on voltage(V_(ON)) through an additional SET operation, allowing V_(ON) to shift above 0 V. The retention time in SET operation was extended to 10^(4) s by optimizing the tunneling layer deposition conditions. The device characterization revealed a significant correlation between V_(ON) and both the WRITE speed and the retention properties of the DT-2T0C, verifying the trade-off between WRITE time and retention time. A long retention time over 1000 s was achieved, even under VHOLD of 0 V.
