Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.展开更多
An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal ...An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal flow of circuit.Then,it converts the bit slice structure to parallel constraints to enable Q place algorithm.The design flow and the main algorithms are introduced.Finally,the satisfied experimental result of the tool compared with the Cadence placement tool SE is discussed.展开更多
文摘Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
文摘An algorithm named DPP is addressed.In it,a new model based on the concept of irregularity degree is founded to evaluate the regularity of cells.It generates the structure regularity of cells by exploiting the signal flow of circuit.Then,it converts the bit slice structure to parallel constraints to enable Q place algorithm.The design flow and the main algorithms are introduced.Finally,the satisfied experimental result of the tool compared with the Cadence placement tool SE is discussed.
