We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital c...We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.展开更多
Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
文摘We present a new hybrid digital pulse-width modulator （DPWM） for digital DC-DC converters that employs a ring-oscillator/counter structure. Based on a temperature/process compensation technique and a novel digital controller, the proposed DPWM can not only offer temperature/process-independent pulse widths, but also operate at a much higher clock frequency than the existing delay-line/counter DPWM structure. Post-simulation results show that with our DPWM, the system clock frequency reaches 156.9MHz while the worst variation,in a temperature range of 0 to 100℃under all process corners,is only± 9.4%.
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
