Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative thr...Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.展开更多
Two kinds of corner effects existing in double-gate （DG） and gate-all-around （GAA） MOSFETs have been investigated by three-dimensional （3D） and two-dimensional （2D） simulations. It is found that the corner eff...Two kinds of corner effects existing in double-gate （DG） and gate-all-around （GAA） MOSFETs have been investigated by three-dimensional （3D） and two-dimensional （2D） simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL （drain induced barrier lowering） effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.展开更多
随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了...随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。展开更多
N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 6...N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.展开更多
本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了...本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道,使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合,有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.展开更多
基金Project supported by the Weapon Equipment Pre-Research Foundation of China(Grant No.9140A11020114ZK34147)the Shanghai Municipal Natural Science Foundation,China(Grant No.15ZR1447100)
文摘Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.
基金Project supported by State Key Fundamental Research Project of China （Grant No 2000036501） and the National Natural Science Foundation of China （Grant No 90207004）.
文摘Two kinds of corner effects existing in double-gate （DG） and gate-all-around （GAA） MOSFETs have been investigated by three-dimensional （3D） and two-dimensional （2D） simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL （drain induced barrier lowering） effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.
文摘随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。
基金Project supported by the National Natural Science Foundation of China （Grant No 60376024）.
文摘N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
文摘本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道,使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合,有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.
