电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,...电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。展开更多
随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线...随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线性度的方法,并以一款分段式10 bit DAC为例,分别采用简码和传统的全码方法验证了它的微分非线性DNL与积分非线性INL。结果表明,简码测试和全码测试得到的DNL与INL曲线趋势一致,但简码测试效率高,仅占全码测试周期的1/8;另外简码测试减小了负载电阻温漂引入的误差,因此相比全码测试线性度的性能提高了0.1-0.2 LSB。展开更多
In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing...In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.展开更多
文摘设计并实现了应用于2.8 G高速DAC芯片的内部测试电路,该电路输出两路线性斜坡信号作为DAC模块的输入数据,DAC模块将其合成为一路线性斜坡信号输出。通过设计实验和多种设计方案优缺点比较,该测试电路最终采用两路并行累加器架构,克服了传统累加器结构无法用于高速电路的固有缺陷。在65 nm工艺下,基于此测试电路设计了测试芯片并进行了流片验证。测试结果表明:测试芯片整体可达到2.8 G SPS的测试速度,实现了对吉赫兹DAC全扫描测试的设计目标。
文摘电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。
文摘随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线性度的方法,并以一款分段式10 bit DAC为例,分别采用简码和传统的全码方法验证了它的微分非线性DNL与积分非线性INL。结果表明,简码测试和全码测试得到的DNL与INL曲线趋势一致,但简码测试效率高,仅占全码测试周期的1/8;另外简码测试减小了负载电阻温漂引入的误差,因此相比全码测试线性度的性能提高了0.1-0.2 LSB。
文摘In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.
