This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear...This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear Equalizer(CTLE),a Variable Gain Amplifier(VGA),an input impedance matching network,a buffer stage,and an output buffer.The single-stage triple-peaking CTLE proposed employs current reuse technique and a multi-feedback structure,enabling the adjustment of peaking in the low,mid,and high-frequency bands.Thus,only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power.The VGA adopts an enhanced structure based on the Gilbert cell,where the gain is manipulated by controlling the gate voltage of MOS transistors.The CTLE undergoes variations in its DC gain during the adjustment process to equalize channel losses.The role of the VGA is to stable the DC gain changes induced by the adjustment of the CTLE.The output buffer adopts two stages,aiming to ensure that the gain does not attenuate excessively while maintaining output impedance matching.The AFE consumes 21.1 mW with a supply voltage of 1.5/1 V.It can provide a maximum boost of 22.5 dB,and the data rate reaches up to 64 Gb/s.Additionally,it features peaking adjustment capabilities in the low,mid,and high-frequency bands.Finally,the measurement demonstrates its ability to effectively equalize a channel with a 12-dB loss at the Nyquist frequency of 16 GHz.展开更多
本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)和2抽头判决反馈均衡器(Decision Feedback Equalizer,DFE)的组合结构来消除信道码间干扰中的前标分量和后...本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)和2抽头判决反馈均衡器(Decision Feedback Equalizer,DFE)的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方(Least Mean Square,LMS)算法电路控制DFE系数的自适应.电路采用IBM 0.13μm Bi CMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm^2,在3.3V的电源电压下,功耗为624m W.展开更多
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62222409 and Grant 62174153.
文摘This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear Equalizer(CTLE),a Variable Gain Amplifier(VGA),an input impedance matching network,a buffer stage,and an output buffer.The single-stage triple-peaking CTLE proposed employs current reuse technique and a multi-feedback structure,enabling the adjustment of peaking in the low,mid,and high-frequency bands.Thus,only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power.The VGA adopts an enhanced structure based on the Gilbert cell,where the gain is manipulated by controlling the gate voltage of MOS transistors.The CTLE undergoes variations in its DC gain during the adjustment process to equalize channel losses.The role of the VGA is to stable the DC gain changes induced by the adjustment of the CTLE.The output buffer adopts two stages,aiming to ensure that the gain does not attenuate excessively while maintaining output impedance matching.The AFE consumes 21.1 mW with a supply voltage of 1.5/1 V.It can provide a maximum boost of 22.5 dB,and the data rate reaches up to 64 Gb/s.Additionally,it features peaking adjustment capabilities in the low,mid,and high-frequency bands.Finally,the measurement demonstrates its ability to effectively equalize a channel with a 12-dB loss at the Nyquist frequency of 16 GHz.
文摘本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)和2抽头判决反馈均衡器(Decision Feedback Equalizer,DFE)的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方(Least Mean Square,LMS)算法电路控制DFE系数的自适应.电路采用IBM 0.13μm Bi CMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm^2,在3.3V的电源电压下,功耗为624m W.
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
