A low voltage bandgap reference with curvature compensation is presented. Using current mode structure, the proposed bandgap circuit has a minimum voltage of 900mV. Compensated through the VEB linearization technique,...A low voltage bandgap reference with curvature compensation is presented. Using current mode structure, the proposed bandgap circuit has a minimum voltage of 900mV. Compensated through the VEB linearization technique, this bandgap reference can reach a temperature coefficient of 10ppmFC from 0 to 150℃. With a 1.1V supply voltage,the supply current is 43μA and the PSRR is 55dB at DC frequency. This bandgap reference has been verified in a UMC 0.18μm mixed mode CMOS technology and occupies 0. 186mm^2 of chip area.展开更多
A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJT...A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.展开更多
A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to VTlnT realized by utilizing voltage to current converters and th...A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to VTlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42 μA.展开更多
A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs...A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.展开更多
文摘A low voltage bandgap reference with curvature compensation is presented. Using current mode structure, the proposed bandgap circuit has a minimum voltage of 900mV. Compensated through the VEB linearization technique, this bandgap reference can reach a temperature coefficient of 10ppmFC from 0 to 150℃. With a 1.1V supply voltage,the supply current is 43μA and the PSRR is 55dB at DC frequency. This bandgap reference has been verified in a UMC 0.18μm mixed mode CMOS technology and occupies 0. 186mm^2 of chip area.
文摘A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.
文摘A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to VTlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42 μA.
基金Project supported by the National Natural Science Foundation of China(No.61176029)the National Twelve-Five Project(No.513***)
文摘A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
