生成式人工智能(AIGC)技术飞速发展,正推动工业设计的理论与实践变革。为厘清该领域的研究热点及演进路径,研究基于文献计量学方法,分别对中国知网(CNKI)和Web of Science(WOS)数据库中的相关文献进行可视化分析。结果表明,国内外研究...生成式人工智能(AIGC)技术飞速发展,正推动工业设计的理论与实践变革。为厘清该领域的研究热点及演进路径,研究基于文献计量学方法,分别对中国知网(CNKI)和Web of Science(WOS)数据库中的相关文献进行可视化分析。结果表明,国内外研究均聚焦“数据驱动设计”与“人机协同”主题,但国内研究侧重本土化与场景化的实践应用,国际研究侧重用户接受度与人机共生研究。未来需推动跨学科方法融合、完善伦理规范与文化适配研究,深化垂直应用场景的实践探索,促进AIGC与工业设计的融合发展。展开更多
This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector...This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.展开更多
文摘生成式人工智能(AIGC)技术飞速发展,正推动工业设计的理论与实践变革。为厘清该领域的研究热点及演进路径,研究基于文献计量学方法,分别对中国知网(CNKI)和Web of Science(WOS)数据库中的相关文献进行可视化分析。结果表明,国内外研究均聚焦“数据驱动设计”与“人机协同”主题,但国内研究侧重本土化与场景化的实践应用,国际研究侧重用户接受度与人机共生研究。未来需推动跨学科方法融合、完善伦理规范与文化适配研究,深化垂直应用场景的实践探索,促进AIGC与工业设计的融合发展。
基金Project supported by the National Nature Science Foundation of China(Nos.61331003,61474108)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2016ZX03001002)
文摘This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.
