The thermo-mechanical reliability of IMCs(Ni_(3)Sn_(4),Cu_(3)Sn,Cu_(6)Sn_(5))solder joints and Sn-3.9Ag-0.6Cu solder joints was investigated systematically in 3D chip stacking structure subjected to an accelerated the...The thermo-mechanical reliability of IMCs(Ni_(3)Sn_(4),Cu_(3)Sn,Cu_(6)Sn_(5))solder joints and Sn-3.9Ag-0.6Cu solder joints was investigated systematically in 3D chip stacking structure subjected to an accelerated thermal cyclic loading based on finite element simulation and Taguchi method.Effects of different control factors,including high temperature,low temperature,dwell time of thermal cyclic loading,and different IMCs on the stress-strain response and fatigue life of solder joints were calculated respectively.The results indicate that maximum stress-strain can be found in the second solder joint on the diagonal of IMC solder joints array;for Sn-3.9Ag-0.6Cu solder joints array,the corner solder joints show the obvious maximum stress-strain,these areas are the crack propagated locations.The stress-strain and fatigue life of solder joints is more sensitive to dwell temperature,especially to high temperature;increasing the high temperature,dwell time,or decreasing the low temperature,can reduce the stress-strain and enlarge the fatigue life of solder joints.Finally,the optimal design in the 3D-IC structure has the combination of the Cu_(6)Sn_(5)/Cu_(3)Sn,373 K high temperature,233 K low temperature,and 10 min dwell time.The fatigue lives of Sn-3.9Ag-0.6Cu under 218-398 K loading in the 3D assembly based on the creep strain are 347.4 cycles,which is in good agreement with experimental results(380 cycles).展开更多
Geant4 Monte Carlo simulation results of the single event upset(SEU)induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported.The SEU cross section for planar and three-dimensional(3D)die-stacked SRAM ...Geant4 Monte Carlo simulation results of the single event upset(SEU)induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported.The SEU cross section for planar and three-dimensional(3D)die-stacked SRAM are calculated.The results show that the SEU cross sections of the planar device and the 3D device are different from each other under low energy proton direct ionization mechanism,but almost the same for the high energy proton.Besides,the multi-bit upset(MBU)ratio and pattern are presented and analyzed.The results indicate that the MBU ratio of the 3D die-stacked device is higher than that of the planar device,and the MBU patterns are more complicated.Finally,the on-orbit upset rate for the 3D die-stacked device and the planar device are calculated by SPACE RADIATION software.The calculation results indicate that no matter what the orbital parameters and shielding conditions are,the on-orbit upset rate of planar device is higher than that of 3D die-stacked device.展开更多
Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harv...Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harvesting devices and power generators encompass a number of non-classical system behaviors or characteristics, such as delivering nondeterministic power density, and these would create hindrance for effectively utilizing the harvested energy. Previously, we have investigated new design methods and tools that are used to enable power adaptive computing and, particularly, catering non-deterministic voltage, which can efficiently utilize ambient energy sources. Also, we developed a co-optimization approach to maximize the computational efficiency from the harvested ambient energy. This paper will provide a review of these methods. Emerging technologies, such as 3D-IC, which would also enable new paradigm of green and high-performance computing, will be also discussed.展开更多
随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoW...随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoWoS-S(chip on wafer on substrate)封装因其高带宽、低延迟及丰富的成功量产案例而被广泛应用于片上系统芯片(SoC-system on chip)与高带宽内存(HBM-high bandwidth memory)的互连。然而,在CoWoS-S技术的硅中介层设计过程中,设计人员将面临严苛的信号完整性与电源完整性的综合挑战。为了解决这些挑战,Cadence作为EDA领域的创新者和领导者,开发了完整的EDA解决方案,以协助设计人员完成硅中介层的设计及签核任务。本文将介绍如何利用Cadence EDA解决方案来高效率地实现CoWoS-S硅中介层的设计与签核,内容聚焦于大电流区域的电源完整性设计以及HBM互连区域的信号完整性设计。展开更多
基金Supported by State Key Lab of Advanced Welding and Joining,Harbin Institute of Technology(Grant No.AWJ-19Z04)Major State Research Development Program of China(Grant No.2019YFF0217400)the Central Plains Science and Technology Innovation Leading Talents Program(Grant No.ZYQR20180030).
文摘The thermo-mechanical reliability of IMCs(Ni_(3)Sn_(4),Cu_(3)Sn,Cu_(6)Sn_(5))solder joints and Sn-3.9Ag-0.6Cu solder joints was investigated systematically in 3D chip stacking structure subjected to an accelerated thermal cyclic loading based on finite element simulation and Taguchi method.Effects of different control factors,including high temperature,low temperature,dwell time of thermal cyclic loading,and different IMCs on the stress-strain response and fatigue life of solder joints were calculated respectively.The results indicate that maximum stress-strain can be found in the second solder joint on the diagonal of IMC solder joints array;for Sn-3.9Ag-0.6Cu solder joints array,the corner solder joints show the obvious maximum stress-strain,these areas are the crack propagated locations.The stress-strain and fatigue life of solder joints is more sensitive to dwell temperature,especially to high temperature;increasing the high temperature,dwell time,or decreasing the low temperature,can reduce the stress-strain and enlarge the fatigue life of solder joints.Finally,the optimal design in the 3D-IC structure has the combination of the Cu_(6)Sn_(5)/Cu_(3)Sn,373 K high temperature,233 K low temperature,and 10 min dwell time.The fatigue lives of Sn-3.9Ag-0.6Cu under 218-398 K loading in the 3D assembly based on the creep strain are 347.4 cycles,which is in good agreement with experimental results(380 cycles).
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11690041 and 11675233)the Fund from the Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C054).
文摘Geant4 Monte Carlo simulation results of the single event upset(SEU)induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported.The SEU cross section for planar and three-dimensional(3D)die-stacked SRAM are calculated.The results show that the SEU cross sections of the planar device and the 3D device are different from each other under low energy proton direct ionization mechanism,but almost the same for the high energy proton.Besides,the multi-bit upset(MBU)ratio and pattern are presented and analyzed.The results indicate that the MBU ratio of the 3D die-stacked device is higher than that of the planar device,and the MBU patterns are more complicated.Finally,the on-orbit upset rate for the 3D die-stacked device and the planar device are calculated by SPACE RADIATION software.The calculation results indicate that no matter what the orbital parameters and shielding conditions are,the on-orbit upset rate of planar device is higher than that of 3D die-stacked device.
基金supported by the National Natural Science Foundation of China under Grant No. 61176025 and No. 61006027
文摘Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harvesting devices and power generators encompass a number of non-classical system behaviors or characteristics, such as delivering nondeterministic power density, and these would create hindrance for effectively utilizing the harvested energy. Previously, we have investigated new design methods and tools that are used to enable power adaptive computing and, particularly, catering non-deterministic voltage, which can efficiently utilize ambient energy sources. Also, we developed a co-optimization approach to maximize the computational efficiency from the harvested ambient energy. This paper will provide a review of these methods. Emerging technologies, such as 3D-IC, which would also enable new paradigm of green and high-performance computing, will be also discussed.
文摘随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoWoS-S(chip on wafer on substrate)封装因其高带宽、低延迟及丰富的成功量产案例而被广泛应用于片上系统芯片(SoC-system on chip)与高带宽内存(HBM-high bandwidth memory)的互连。然而,在CoWoS-S技术的硅中介层设计过程中,设计人员将面临严苛的信号完整性与电源完整性的综合挑战。为了解决这些挑战,Cadence作为EDA领域的创新者和领导者,开发了完整的EDA解决方案,以协助设计人员完成硅中介层的设计及签核任务。本文将介绍如何利用Cadence EDA解决方案来高效率地实现CoWoS-S硅中介层的设计与签核,内容聚焦于大电流区域的电源完整性设计以及HBM互连区域的信号完整性设计。
