A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The ...A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.展开更多
This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the ...This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.展开更多
1000 MPa级高强钢在水电领域的应用已日趋成熟,但国内相应高性能焊材的研发较少,高强度熔敷金属保持低温高韧性是研发难点之一.通过添加Ce元素优化熔敷金属,并利用扫描电子显微镜(scanning electron microscope,SEM)、透射电子显微镜(tr...1000 MPa级高强钢在水电领域的应用已日趋成熟,但国内相应高性能焊材的研发较少,高强度熔敷金属保持低温高韧性是研发难点之一.通过添加Ce元素优化熔敷金属,并利用扫描电子显微镜(scanning electron microscope,SEM)、透射电子显微镜(transmission electron microscope,TEM)、高温激光共聚焦扫描显微镜(confocal laser scanning microscope,CLSM)等微观组织表征方法,研究了Ce含量对1000 MPa级高强钢埋弧焊熔敷金属组织强韧性及组织演变规律的影响.结果表明,Ce含量为0.02%时,抗拉和屈服强度分别提高3.7%和17.2%,此时强韧匹配效果最好,低温冲击韧性整体提升,Ce含量为0.01%时提升最大,-40℃和-60℃环境下分别为24.3%和42.2%.微观组织方面,Ce可细化晶粒,使M-A组元分布更弥散,增强组织韧性;含量为0.04%时会使块状铁素体和针状铁素体尺寸变大、大尺寸晶粒增多,影响抗拉强度.演变机理上,Ce与C协同富集引发晶格畸变促进M-A组元生成,含量为0.02%时使残余奥氏体含量增加,借助相变诱发塑性(transformationinduced plasticity,TRIP)效应提升塑性变形能力,促进下贝氏体转变实现强韧性协同提升;0.04%的Ce则导致晶界偏析加剧,形成含Ce脆性相析出物,降低奥氏体稳定性,使冲击韧性相对于0.02%时劣化.展开更多
文摘A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.
基金the National Science Foundation for Creative Research Groups （60521002）Shanghai Natural Science Foundation （037062022）.
文摘This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.
