A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 n...With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.展开更多
A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smalle...A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.展开更多
How to design a multicast key management system with high performance is a hot issue now. This paper will apply the idea of hierarchical data processing to construct a common analytic model based on directed logical k...How to design a multicast key management system with high performance is a hot issue now. This paper will apply the idea of hierarchical data processing to construct a common analytic model based on directed logical key tree and supply two important metrics to this problem： re-keying cost and key storage cost. The paper gives the basic theory to the hierarchical data processing and the analyzing model to multieast key management based on logical key tree. It has been proved that the 4-ray tree has the best performance in using these metrics. The key management problem is also investigated based on user probability model, and gives two evaluating parameters to re-keying and key storage cost.展开更多
Modal logic characterization in a higher-order setting is usually not a trivial task because higher-order process-passing is quite different from first-order name-passing. We study the logical characterization of high...Modal logic characterization in a higher-order setting is usually not a trivial task because higher-order process-passing is quite different from first-order name-passing. We study the logical characterization of higherorder processes constrained by linearity. Linearity respects resource-sensitiveness and does not allow processes to duplicate themselves arbitrarily. We provide a modal logic that characterizes linear higher-order processes,particularly the bisimulation called local bisimulation over them. More importantly, the logic has modalities for higher-order actions downscaled to resembling first-order ones in Hennessy-Milner logic, based on a formulation exploiting the linearity of processes.展开更多
With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependenc...With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.展开更多
A formal methodology is proposed to reduce the amount of information displayed to remote human operators at interfaces to large-scale process control plants of a certain type. The reduction proceeds in two stages. In ...A formal methodology is proposed to reduce the amount of information displayed to remote human operators at interfaces to large-scale process control plants of a certain type. The reduction proceeds in two stages. In the first stage, minimal reduced subsets of components, which give full information about the state of the whole system, are generated by determining functional dependencies between components. This is achieved by using a temporal logic proof obligation to check whether the state of all components can be inferred from the state of components in a subset in specified situations that the human operator needs to detect, with respect to a finite state machine model of the system and other human operator behavior. Generation of reduced subsets is automated with the help of a temporal logic model checker. The second stage determines the interconnections between components to be displayed in the reduced system so that the natural overall graphical structure of the system is maintained. A formal definition of an aesthetic for the required subgraph of a graph representation of the full system, containing the reduced subset of components, is given for this purpose. The methodology is demonstrated by a case study.展开更多
Test of consistency is critical for the analytic hierarchy process(AHP) methodology. When a pairwise comparison matrix(PCM) fails the consistency test, the decision maker(DM) needs to make revisions. The state of the ...Test of consistency is critical for the analytic hierarchy process(AHP) methodology. When a pairwise comparison matrix(PCM) fails the consistency test, the decision maker(DM) needs to make revisions. The state of the art focuses on changing a single entry or creating a new matrix based on the original inconsistent matrix so that the modified matrix can satisfy the consistency requirement. However, we have noticed that the reason that causes inconsistency is not only numerical inconsistency, but also logical inconsistency, which may play a more important role in the whole inconsistency. Therefore, to realize satisfactory consistency, first of all, we should change some entries that form a directed circuit to make the matrix logically consistent, and then adjust other entries within acceptable deviations to make the matrix numerically consistent while preserving most of the original comparison information. In this paper, we firstly present some definitions and theories, based on which two effective methods are provided to identify directed circuits. Four optimization models are proposed to adjust the original inconsistent matrix. Finally, illustrative examples and comparison studies show the effectiveness and feasibility of our method.展开更多
Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image pro...Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image processing system.The theoretical analysis,andthe simulations for the building block circuits such as D/A converters,comparator and so on aregiven.The layout design of the whole circuit are also given.The binary image processing can berealized by using the VTL circuit combined with its external auxiliary circuits.展开更多
Phase Shifting And Logical Moire (PSALM) is a kind of computer image processing method which can be used in phase measurement and to obtain the shape, deformation and strain distribution of an object.This paper presen...Phase Shifting And Logical Moire (PSALM) is a kind of computer image processing method which can be used in phase measurement and to obtain the shape, deformation and strain distribution of an object.This paper presents the structure and working procedure of a 2D phase measurement PSALM2D program and its application. When analyzing moire interferometric fringes,we can obtain 2D distribution of displacement and strain.When it is used in reflection moire we can measure the slope of a specimen.Satisfactory visualization and quantitative results are given by PSALM2D.展开更多
Different programming languages can be used for discrete, abstract and process-oriented programming. Depending on the application, there exist additional requirements, which are not fulfilled by every programming lang...Different programming languages can be used for discrete, abstract and process-oriented programming. Depending on the application, there exist additional requirements, which are not fulfilled by every programming language. Flexible programming and maintainability are especially important requirements for process engineers. In this paper, the programming languages Activity Diagram, State Chart Diagram and Sequential Function Chart are compared and evaluated with regard to these requirements. This evaluation is based on the principles of cognitive effectiveness and cognitive dimensions. The aim of this paper is to identify the programming language suited best for controlling sequential processes, e.g. thermomechanical or batch processes.展开更多
Drought conditions at a given location evolve randomly through time and are typically characterized by severity and duration. Researchers interested in modeling the economic effects of drought on agriculture or other ...Drought conditions at a given location evolve randomly through time and are typically characterized by severity and duration. Researchers interested in modeling the economic effects of drought on agriculture or other water users often capture the stochastic nature of drought and its conditions via multiyear, stochastic economic models. Three major sources of uncertainty in application of a multiyear discrete stochastic model to evaluate user preparedness and response to drought are: (1) the assumption of independence of yearly weather conditions, (2) linguistic vagueness in the definition of drought itself, and (3) the duration of drought. One means of addressing these uncertainties is to re-cast drought as a stochastic, multiyear process using a “fuzzy” semi-Markov process. In this paper, we review “crisp” versus “fuzzy” representations of drought and show how fuzzy semi-Markov processes can aid researchers in developing more robust multiyear, discrete stochastic models.展开更多
Models for the design of assembly processes are considered. Various models for the voice control of an industrial robot are considered: a logical model, semantic networks, a frame model and Petri nets. It is shown tha...Models for the design of assembly processes are considered. Various models for the voice control of an industrial robot are considered: a logical model, semantic networks, a frame model and Petri nets. It is shown that this set of models allows describing the process of designing the technological process for an industrial robot. The logical model of the technological process allows you to define logical relationships. A model based on semantic networks describes the relationship between assembly units in a detail. This allows you to determine the order and method of registration, as well as the mutual orientation of assembly units in the product. The frame model provides the ability to streamline the execution of the build process. A model based on Petri nets allows one to describe the type and sequence of technological transitions. Based on the proposed models, a method of voice control for an industrial robot is developed. The basic principles of voice control for an industrial robot are considered.展开更多
A prodouct modeling and a process planning that are two essential basses of realizing concurrent engineering are investigated , a logical modeling technique , grammar representation scheme of technology knowledge and...A prodouct modeling and a process planning that are two essential basses of realizing concurrent engineering are investigated , a logical modeling technique , grammar representation scheme of technology knowledge and architecture of expert system for process planning within con- current engineering environment are proposed. They have been utilized in a real reaserch project.展开更多
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
文摘With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.
基金Project(10039239) supported by the Industrial Strategic Technology Development Program Funded by the Ministry of Knowledge Economy, Korea
文摘A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.
基金Supported by the National High-Technology Re-search and Development Programof China(2001AA115300) the Na-tional Natural Science Foundation of China (69874038) ,the Nat-ural Science Foundation of Liaoning Province(20031018)
文摘How to design a multicast key management system with high performance is a hot issue now. This paper will apply the idea of hierarchical data processing to construct a common analytic model based on directed logical key tree and supply two important metrics to this problem： re-keying cost and key storage cost. The paper gives the basic theory to the hierarchical data processing and the analyzing model to multieast key management based on logical key tree. It has been proved that the 4-ray tree has the best performance in using these metrics. The key management problem is also investigated based on user probability model, and gives two evaluating parameters to re-keying and key storage cost.
基金the National Natural Science Foundation of China(Nos.61202023,61261130589 and61173048)the PACE Project(No.12IS02001)the Specialized Research Fund for the Doctoral Program of Higher Edueation of China(No.20120073120031)
文摘Modal logic characterization in a higher-order setting is usually not a trivial task because higher-order process-passing is quite different from first-order name-passing. We study the logical characterization of higherorder processes constrained by linearity. Linearity respects resource-sensitiveness and does not allow processes to duplicate themselves arbitrarily. We provide a modal logic that characterizes linear higher-order processes,particularly the bisimulation called local bisimulation over them. More importantly, the logic has modalities for higher-order actions downscaled to resembling first-order ones in Hennessy-Milner logic, based on a formulation exploiting the linearity of processes.
基金supported by the National Natural Science Foundation of China (No. 61502043, No. 61132001)Beijing Natural Science Foundation (No. 4162042)BeiJing Talents Fund (No. 2015000020124G082)
文摘With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.
基金This work was supported by the Royal Society in the UK (No.2004R1)An initial study appeared in Proceedings of IEEE International Conference on Systems,Man and Cybernetics,the Hague,Netherlands,pp.124-129,2004.
文摘A formal methodology is proposed to reduce the amount of information displayed to remote human operators at interfaces to large-scale process control plants of a certain type. The reduction proceeds in two stages. In the first stage, minimal reduced subsets of components, which give full information about the state of the whole system, are generated by determining functional dependencies between components. This is achieved by using a temporal logic proof obligation to check whether the state of all components can be inferred from the state of components in a subset in specified situations that the human operator needs to detect, with respect to a finite state machine model of the system and other human operator behavior. Generation of reduced subsets is automated with the help of a temporal logic model checker. The second stage determines the interconnections between components to be displayed in the reduced system so that the natural overall graphical structure of the system is maintained. A formal definition of an aesthetic for the required subgraph of a graph representation of the full system, containing the reduced subset of components, is given for this purpose. The methodology is demonstrated by a case study.
基金supported by the National Natural Science Foundation of China(61601501 61502521)
文摘Test of consistency is critical for the analytic hierarchy process(AHP) methodology. When a pairwise comparison matrix(PCM) fails the consistency test, the decision maker(DM) needs to make revisions. The state of the art focuses on changing a single entry or creating a new matrix based on the original inconsistent matrix so that the modified matrix can satisfy the consistency requirement. However, we have noticed that the reason that causes inconsistency is not only numerical inconsistency, but also logical inconsistency, which may play a more important role in the whole inconsistency. Therefore, to realize satisfactory consistency, first of all, we should change some entries that form a directed circuit to make the matrix logically consistent, and then adjust other entries within acceptable deviations to make the matrix numerically consistent while preserving most of the original comparison information. In this paper, we firstly present some definitions and theories, based on which two effective methods are provided to identify directed circuits. Four optimization models are proposed to adjust the original inconsistent matrix. Finally, illustrative examples and comparison studies show the effectiveness and feasibility of our method.
文摘Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image processing system.The theoretical analysis,andthe simulations for the building block circuits such as D/A converters,comparator and so on aregiven.The layout design of the whole circuit are also given.The binary image processing can berealized by using the VTL circuit combined with its external auxiliary circuits.
文摘Phase Shifting And Logical Moire (PSALM) is a kind of computer image processing method which can be used in phase measurement and to obtain the shape, deformation and strain distribution of an object.This paper presents the structure and working procedure of a 2D phase measurement PSALM2D program and its application. When analyzing moire interferometric fringes,we can obtain 2D distribution of displacement and strain.When it is used in reflection moire we can measure the slope of a specimen.Satisfactory visualization and quantitative results are given by PSALM2D.
文摘Different programming languages can be used for discrete, abstract and process-oriented programming. Depending on the application, there exist additional requirements, which are not fulfilled by every programming language. Flexible programming and maintainability are especially important requirements for process engineers. In this paper, the programming languages Activity Diagram, State Chart Diagram and Sequential Function Chart are compared and evaluated with regard to these requirements. This evaluation is based on the principles of cognitive effectiveness and cognitive dimensions. The aim of this paper is to identify the programming language suited best for controlling sequential processes, e.g. thermomechanical or batch processes.
文摘Drought conditions at a given location evolve randomly through time and are typically characterized by severity and duration. Researchers interested in modeling the economic effects of drought on agriculture or other water users often capture the stochastic nature of drought and its conditions via multiyear, stochastic economic models. Three major sources of uncertainty in application of a multiyear discrete stochastic model to evaluate user preparedness and response to drought are: (1) the assumption of independence of yearly weather conditions, (2) linguistic vagueness in the definition of drought itself, and (3) the duration of drought. One means of addressing these uncertainties is to re-cast drought as a stochastic, multiyear process using a “fuzzy” semi-Markov process. In this paper, we review “crisp” versus “fuzzy” representations of drought and show how fuzzy semi-Markov processes can aid researchers in developing more robust multiyear, discrete stochastic models.
文摘Models for the design of assembly processes are considered. Various models for the voice control of an industrial robot are considered: a logical model, semantic networks, a frame model and Petri nets. It is shown that this set of models allows describing the process of designing the technological process for an industrial robot. The logical model of the technological process allows you to define logical relationships. A model based on semantic networks describes the relationship between assembly units in a detail. This allows you to determine the order and method of registration, as well as the mutual orientation of assembly units in the product. The frame model provides the ability to streamline the execution of the build process. A model based on Petri nets allows one to describe the type and sequence of technological transitions. Based on the proposed models, a method of voice control for an industrial robot is developed. The basic principles of voice control for an industrial robot are considered.
文摘A prodouct modeling and a process planning that are two essential basses of realizing concurrent engineering are investigated , a logical modeling technique , grammar representation scheme of technology knowledge and architecture of expert system for process planning within con- current engineering environment are proposed. They have been utilized in a real reaserch project.
