Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of...Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.展开更多
基金supported by the Technology Innovation Program(Grant Nos.20017382 and 20023023)funded by the Ministry of Trade,Industry&Energy(MOTIE,Republic of Korea)supported by a National Research Foundation of Korea(NRF)grant funded by the Korean Government(MSIT)(Grant No.RS-2023-00260527).
文摘Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.
