A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the convent...A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-ba...Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.展开更多
设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态...设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.展开更多
基金Project supported by the 2nd Stage of Brain KoreaProject supported by the Korea Research Foundation
文摘A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
文摘Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.
文摘设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.
