The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because...The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.展开更多
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length a...By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.展开更多
The material and electrical properties of HfO 2 hi gh-k gate dielectric are reported.In the first part,the band alignment of H fO 2 and (HfO 2) x(Al 2O 3) 1-x to (100)Si substrate and thei r thermal stability are stud...The material and electrical properties of HfO 2 hi gh-k gate dielectric are reported.In the first part,the band alignment of H fO 2 and (HfO 2) x(Al 2O 3) 1-x to (100)Si substrate and thei r thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO 2) x(Al 2O 3) 1-x,the valence band offset, and the conduction band offset between (HfO 2) x(Al 2O 3) 1-x and the Si substrate as functions of x are obtained based on the XPS results .Our XPS results also demonstrate that both the thermal stability and the resist ance to oxygen diffusion of HfO 2 are improved by adding Al to form Hf aluminat es.In the second part,a thermally stable and high quality HfN/HfO 2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage, and work function (close to Si mid-gap) of HfN/HfO 2 gate stack are demonstrat ed even after 1000℃ post-metal annealing(PMA),which is attributed to the super ior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/ HfO 2 interface.Therefore,even without surface nitridation prior to HfO 2 depo sition,the EOT of HfN/HfO 2 gate stack has been successfully scaled down to les s than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.T he last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO 2 gate dielectric.The excellent thermal stability of the HfN/HfO 2 gate stack enables its use in high temperature CMOS processes.Th e replacement of HfN with other metal gate materials with work functions adequat e for n- and p-MOS is facilitated by a high etch selectivity of HfN with respe ct to HfO 2,without any degradation to the EOT,gate leakage,or TDDB characteris tics of HfO 2.展开更多
The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the ...The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.展开更多
基于等腰劈光学等倾干涉原理,利用CMOS(complementary metal oxide semiconductor,互补金属氧化物半导体)图像传感器,设计了一种可测量流体折射率微小变化的传感器系统。该系统使用具有高频率像素时钟的CMOS图像传感器对等腰劈中出射光...基于等腰劈光学等倾干涉原理,利用CMOS(complementary metal oxide semiconductor,互补金属氧化物半导体)图像传感器,设计了一种可测量流体折射率微小变化的传感器系统。该系统使用具有高频率像素时钟的CMOS图像传感器对等腰劈中出射光信号进行测量,将携带信息的光信号转换成电信号,再经过一块现场可编程门阵列(field programmable gate array,FPGA)芯片采集数字图像,通过极值计数法处理数据获得光学信息,从而计算流体折射率微变量。该传感器系统的理论测量精度达2.75×10^-6,可应用于大气测量和材料研究等领域。展开更多
随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行...随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明:边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。展开更多
利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效...利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。展开更多
Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the variou...Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.展开更多
The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series ...The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.展开更多
基金support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130)National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010)+3 种基金Ministry of Science and Technology of China (Grant No.2009CB929503)Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4)the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education MinistryNational Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)
文摘The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.
文摘By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
文摘The material and electrical properties of HfO 2 hi gh-k gate dielectric are reported.In the first part,the band alignment of H fO 2 and (HfO 2) x(Al 2O 3) 1-x to (100)Si substrate and thei r thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO 2) x(Al 2O 3) 1-x,the valence band offset, and the conduction band offset between (HfO 2) x(Al 2O 3) 1-x and the Si substrate as functions of x are obtained based on the XPS results .Our XPS results also demonstrate that both the thermal stability and the resist ance to oxygen diffusion of HfO 2 are improved by adding Al to form Hf aluminat es.In the second part,a thermally stable and high quality HfN/HfO 2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage, and work function (close to Si mid-gap) of HfN/HfO 2 gate stack are demonstrat ed even after 1000℃ post-metal annealing(PMA),which is attributed to the super ior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/ HfO 2 interface.Therefore,even without surface nitridation prior to HfO 2 depo sition,the EOT of HfN/HfO 2 gate stack has been successfully scaled down to les s than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.T he last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO 2 gate dielectric.The excellent thermal stability of the HfN/HfO 2 gate stack enables its use in high temperature CMOS processes.Th e replacement of HfN with other metal gate materials with work functions adequat e for n- and p-MOS is facilitated by a high etch selectivity of HfN with respe ct to HfO 2,without any degradation to the EOT,gate leakage,or TDDB characteris tics of HfO 2.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA010601)
文摘The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.
文摘随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明:边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。
文摘利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。
基金supported by the National Natural Science Foundation of China(51172009,51172013 and 11074020)Program for New Century Excellent Talents in University(NCET-08-0029)+1 种基金Hong Kong Research Grants Council(RGC)General Research Funds(GRF)(CityU112510)City University of Hong Kong Strategic Research Grant(SRG)(7008009)
文摘Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.
基金Project supported by the National High Technology Research and Development Program(863 Program)of China(No.SS2015AA010601)the National Natural Science Foundation of China(Nos.61176091+1 种基金61306129)the Opening Project of the Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.
