This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calcul...This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.展开更多
Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach...Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been...Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been investigated by experimental method. The welding power source used for the research is an inverter with a special current waveform control. It is shown that the spatter decreases at first then increases with each increase of the low current period, current increase rate and the maximum current limit. The test results are provided for welding of 1 mm and 3 mm mild steel at speed of 1.2 m/min. The stable GMA W-S process under high speed welding condition has been achieved by optimizing the parameters.展开更多
As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design f...As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.展开更多
针对高速铁电测试中采集卡量程不足导致的信号失真问题,本文提出了一种基于动态补偿的信号调理系统。通过LabVIEW平台,结合脉冲发生器、信号调理电路和ADQ32高速采集卡等硬件,构建了可编程增益放大器(Programmable Gain Amplifier,PGA)...针对高速铁电测试中采集卡量程不足导致的信号失真问题,本文提出了一种基于动态补偿的信号调理系统。通过LabVIEW平台,结合脉冲发生器、信号调理电路和ADQ32高速采集卡等硬件,构建了可编程增益放大器(Programmable Gain Amplifier,PGA)与可变电阻协同控制架构,从而实时检测采集信号幅值并动态切换增益和阻抗,实现动态范围内信号的完整调理。本文以超快铁电存储器测试中的瞬态串联电阻分压为研究对象,信号源发出高频电脉冲信号,施加至铁电存储器器件,随后返回的电信号经信号调理电路被高速采集卡采集,最后LabVIEW对采集到的电信号进行分析反馈,自动调整信号调理电路的增益和阻抗。实验表明,该系统在不同频率(1 Hz~100 MHz)下都能有效地对采集信号进行动态调理,为宽场强范围内超快铁电存储器的性能表征提供了有效的信号预处理手段。展开更多
文摘This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.
文摘Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
文摘Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been investigated by experimental method. The welding power source used for the research is an inverter with a special current waveform control. It is shown that the spatter decreases at first then increases with each increase of the low current period, current increase rate and the maximum current limit. The test results are provided for welding of 1 mm and 3 mm mild steel at speed of 1.2 m/min. The stable GMA W-S process under high speed welding condition has been achieved by optimizing the parameters.
文摘As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.
文摘针对高速铁电测试中采集卡量程不足导致的信号失真问题,本文提出了一种基于动态补偿的信号调理系统。通过LabVIEW平台,结合脉冲发生器、信号调理电路和ADQ32高速采集卡等硬件,构建了可编程增益放大器(Programmable Gain Amplifier,PGA)与可变电阻协同控制架构,从而实时检测采集信号幅值并动态切换增益和阻抗,实现动态范围内信号的完整调理。本文以超快铁电存储器测试中的瞬态串联电阻分压为研究对象,信号源发出高频电脉冲信号,施加至铁电存储器器件,随后返回的电信号经信号调理电路被高速采集卡采集,最后LabVIEW对采集到的电信号进行分析反馈,自动调整信号调理电路的增益和阻抗。实验表明,该系统在不同频率(1 Hz~100 MHz)下都能有效地对采集信号进行动态调理,为宽场强范围内超快铁电存储器的性能表征提供了有效的信号预处理手段。
