为提升片上静电(Electrostatic Discharge,ESD)防护性能,基于双阱0.18μm CMOS工艺开发了一种级联二极管结构。所开发的结构采用分布式布局,并存在寄生的硅控整流器(Silicon Control Rectifier,SCR)静电泄放路径。由于分布式布局更好的...为提升片上静电(Electrostatic Discharge,ESD)防护性能,基于双阱0.18μm CMOS工艺开发了一种级联二极管结构。所开发的结构采用分布式布局,并存在寄生的硅控整流器(Silicon Control Rectifier,SCR)静电泄放路径。由于分布式布局更好的散热性,所提出结构的鲁棒性提高了约20%。一旦被ESD脉冲所触发,新结构中寄生的SCR将主导ESD电流的泄放,因此所提出结构显著增强了ESD电流处理能力。为评估其可行性和ESD防护特性,对典型结构(DS_(typ))和所提出结构(DS_(new))的两种级联二极管开展了TCAD仿真、传输线脉冲(Transmission Line Pulse,TLP)测试等实验验证。结果表明,较之DS_(typ),DS_(new)具有两条ESD电流路径、更大的失效电流、更低的导通电阻、更低的漏电流和更低的寄生电容等特性。由于其出色的综合性能,新结构是微纳尺度片上I/O ESD防护应用更为可行的解决方案。展开更多
Based on the existing equivalent formula of the transmission line pulse(TLP)and IEC 61000-4-2 stresses,the authors propose an analysis method of the system-level model with TLP stress as an input.Compared with the tra...Based on the existing equivalent formula of the transmission line pulse(TLP)and IEC 61000-4-2 stresses,the authors propose an analysis method of the system-level model with TLP stress as an input.Compared with the traditional analysis method under system-level IEC stress,the proposed method solves the issue that the calculation of the residual energy flowing into the device under test(DUT)is not accurate enough.Meanwhile,the prediction ability for the failure of the DUT is promoted.This work predicts the failure of the DUT under the mentioned two stresses through SPICE simulation.Furthermore,this work shows the validation through the measured results of the relevant printed circuit boards(PCBs),which confirms the promotion of the aforesaid prediction ability.展开更多
文摘为提升片上静电(Electrostatic Discharge,ESD)防护性能,基于双阱0.18μm CMOS工艺开发了一种级联二极管结构。所开发的结构采用分布式布局,并存在寄生的硅控整流器(Silicon Control Rectifier,SCR)静电泄放路径。由于分布式布局更好的散热性,所提出结构的鲁棒性提高了约20%。一旦被ESD脉冲所触发,新结构中寄生的SCR将主导ESD电流的泄放,因此所提出结构显著增强了ESD电流处理能力。为评估其可行性和ESD防护特性,对典型结构(DS_(typ))和所提出结构(DS_(new))的两种级联二极管开展了TCAD仿真、传输线脉冲(Transmission Line Pulse,TLP)测试等实验验证。结果表明,较之DS_(typ),DS_(new)具有两条ESD电流路径、更大的失效电流、更低的导通电阻、更低的漏电流和更低的寄生电容等特性。由于其出色的综合性能,新结构是微纳尺度片上I/O ESD防护应用更为可行的解决方案。
文摘Based on the existing equivalent formula of the transmission line pulse(TLP)and IEC 61000-4-2 stresses,the authors propose an analysis method of the system-level model with TLP stress as an input.Compared with the traditional analysis method under system-level IEC stress,the proposed method solves the issue that the calculation of the residual energy flowing into the device under test(DUT)is not accurate enough.Meanwhile,the prediction ability for the failure of the DUT is promoted.This work predicts the failure of the DUT under the mentioned two stresses through SPICE simulation.Furthermore,this work shows the validation through the measured results of the relevant printed circuit boards(PCBs),which confirms the promotion of the aforesaid prediction ability.
