为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该...为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该电路结构简单,晶体管数量少。由于使用了AB类的缓冲器,因此输出电流不受偏置电流的影响,并且静态电流小。采用SMIC 0.18μm工艺对电路进行仿真,仿真结果表明在1.8 V电源电压、全电压摆幅下,能在0.56μs的建立时间内驱动1 n F的电容负载,同时静态电流只有5μA,可用于液晶显示器的列驱动。展开更多
This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with...This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.展开更多
文摘为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该电路结构简单,晶体管数量少。由于使用了AB类的缓冲器,因此输出电流不受偏置电流的影响,并且静态电流小。采用SMIC 0.18μm工艺对电路进行仿真,仿真结果表明在1.8 V电源电压、全电压摆幅下,能在0.56μs的建立时间内驱动1 n F的电容负载,同时静态电流只有5μA,可用于液晶显示器的列驱动。
基金supported by the National Found for Fostering Talents of Basic Science,China(No.J0730318)the National Science and Technology Maior Project,China(Nos.J2009ZX03007-001-03,2010ZX03007-002-03)
文摘This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
