为解决不间断电源(Uninterruptible Power Supply,UPS)切换过程中发射机监控通信短暂中断的问题,分析电压暂降、谐波干扰及电磁辐射三大成因,提出系统性的解决方案,包括针对性防护措施和数据补发机制。研究结果表明,采用超级电容缓冲、...为解决不间断电源(Uninterruptible Power Supply,UPS)切换过程中发射机监控通信短暂中断的问题,分析电压暂降、谐波干扰及电磁辐射三大成因,提出系统性的解决方案,包括针对性防护措施和数据补发机制。研究结果表明,采用超级电容缓冲、有源滤波、屏蔽敷设等措施可有效提升通信稳定性,结合滑动窗口协议可实现数据的完整恢复。展开更多
Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializ...Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializer/deserializer(SerDes)standards,but NRZ modulation remains predominant in industrial applications.This paper introduces a UMC 28 nm CMOS-based parallel configurable forward feedback equalization(FFE)dual-mode high-speed SerDes transmitter supporting 7-bit resolution with data rates of 56 Gb∙s^(-1)NRZ and 112 Gb∙s^(-1)PAM4,utilizing a hybrid architecture that integrates digital signal processing(DSP)with digital-to-analog conversion(DAC).The design processes parallel input signals and eight stored 8-bit tap coefficients through a configurable FFE multiplier module and parallel carry adder module,while achieving low-power serialization via low-speed 16∶4 multiplexers(MUXs)with two different 2∶1 MUXs and high-speed 4∶1 MUXs.A source series termination(SST)output network structure enhances lower power dissipation and higher output swing.Simulation results show that,under a 1.05 V supply voltage and a channel loss of 19.21 dB at 28 GHz,the output 56 Gb∙s^(-1)NRZ eye diagram has an eye height of 70.11 mV and an eye width of 12.16 ps(0.68 UI).The output 112 Gb∙s^(-1)PAM4 eye diagram has an eye height of 20.07 mV and an eye width of 7.49 ps(0.42 UI).The layout area of the dual-mode transmitter is 0.079 mm^(2),and the total circuit power consumption is 74.48 mW(energy efficiency is 1.33/0.67 pJ∙bit-1).展开更多
基于FPGA的数字基带系统是超高频频段射频识别读写器中的关键部分。根据EPCglobalClass 1 Gen 2标准,用Verilog语言编写了脉冲间隔编码模块和双相空号解码模块,并用C语言编写了其驱动程序,生成组件模块。组件作为Nios II嵌入系统的模块...基于FPGA的数字基带系统是超高频频段射频识别读写器中的关键部分。根据EPCglobalClass 1 Gen 2标准,用Verilog语言编写了脉冲间隔编码模块和双相空号解码模块,并用C语言编写了其驱动程序,生成组件模块。组件作为Nios II嵌入系统的模块,可以重复使用。对于应用程序开发者,不用了解硬件结构就可以使用标准C函数操作组件,使得开发简便快捷,节省了时间和成本。展开更多
文摘为解决不间断电源(Uninterruptible Power Supply,UPS)切换过程中发射机监控通信短暂中断的问题,分析电压暂降、谐波干扰及电磁辐射三大成因,提出系统性的解决方案,包括针对性防护措施和数据补发机制。研究结果表明,采用超级电容缓冲、有源滤波、屏蔽敷设等措施可有效提升通信稳定性,结合滑动窗口协议可实现数据的完整恢复。
基金Supported by the National Key R&D Program Broadband Communications and New Network Key Special Project(No.2019YFB1803600).
文摘Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializer/deserializer(SerDes)standards,but NRZ modulation remains predominant in industrial applications.This paper introduces a UMC 28 nm CMOS-based parallel configurable forward feedback equalization(FFE)dual-mode high-speed SerDes transmitter supporting 7-bit resolution with data rates of 56 Gb∙s^(-1)NRZ and 112 Gb∙s^(-1)PAM4,utilizing a hybrid architecture that integrates digital signal processing(DSP)with digital-to-analog conversion(DAC).The design processes parallel input signals and eight stored 8-bit tap coefficients through a configurable FFE multiplier module and parallel carry adder module,while achieving low-power serialization via low-speed 16∶4 multiplexers(MUXs)with two different 2∶1 MUXs and high-speed 4∶1 MUXs.A source series termination(SST)output network structure enhances lower power dissipation and higher output swing.Simulation results show that,under a 1.05 V supply voltage and a channel loss of 19.21 dB at 28 GHz,the output 56 Gb∙s^(-1)NRZ eye diagram has an eye height of 70.11 mV and an eye width of 12.16 ps(0.68 UI).The output 112 Gb∙s^(-1)PAM4 eye diagram has an eye height of 20.07 mV and an eye width of 7.49 ps(0.42 UI).The layout area of the dual-mode transmitter is 0.079 mm^(2),and the total circuit power consumption is 74.48 mW(energy efficiency is 1.33/0.67 pJ∙bit-1).
文摘基于FPGA的数字基带系统是超高频频段射频识别读写器中的关键部分。根据EPCglobalClass 1 Gen 2标准,用Verilog语言编写了脉冲间隔编码模块和双相空号解码模块,并用C语言编写了其驱动程序,生成组件模块。组件作为Nios II嵌入系统的模块,可以重复使用。对于应用程序开发者,不用了解硬件结构就可以使用标准C函数操作组件,使得开发简便快捷,节省了时间和成本。
