摘要
文章详细论述了设计8051中断系统的方法和过程。采用自顶向下的结构化设计方法,用VHDL语言描述系统中的各元件,并进行软件仿真。最后,将此系统与8051其他模块相结合构成整体的8051系统,搭建FPGA测试台,对中断系统进行全面的测试。
This paper illustrates the method and process of designing the8051's timing /counting system in detail.The top down structure design method is adopted,each entity is described with VHDL,and the description is simulated by software.Finally,this system is combined with other models to compose a whole8051system,and generate a FPGA test platform,on which the interruption system is tested entirely.
出处
《计算机工程与应用》
CSCD
北大核心
2004年第12期122-124,232,共4页
Computer Engineering and Applications
基金
上海市教委基金项目"VHDL硬件描述语言的应用研究"(编号:教委2001第66号01A05)
关键词
VHDL
中断
仿真
VHDL,Interruption,Simulation
