期刊文献+

一种数字域自校正流水线模数转换器改进结构 被引量:1

An Improved Digitally Self-Calibrated Pipeline A/D Converter
在线阅读 下载PDF
导出
摘要 研究了对流水线模数转换器级间增益误差进行补偿的数字域自校正算法,提出了一种适用于数字域自校正的改进的流水线结构.该结构通过对参考电压的调整,避免了以往自校正结构中产生丢失码字、降低输入范围的现象.结果表明,校正后系统的线性度有了大幅度的提升. A new digitally self-calibration algorithm was investigated to compensate interstage gain errors in pipeline analog digital converter (ADC). An improved pipeline ADC structure was introduced which is more adapted to the digital self-calibration algorithm. Missing code and missing decision levels can be eliminated by adjusting reference voltage, and the effect of non-linearity is apparently improved.
出处 《上海交通大学学报》 EI CAS CSCD 北大核心 2004年第5期738-742,746,共6页 Journal of Shanghai Jiaotong University
关键词 流水线模数转换器 数字域自校正 线性度 pipeline analog digital converter (ADC) digital calibration linearity
  • 相关文献

参考文献7

  • 1Karanicolas A N,Lee H-S,Barcania K L.A 15-b 1-M sample/s digitally self-calibrated pipeline ADC [J].IEEE JSSC,1993,28(12):1207-1215.
  • 2Lee S H,Song B S.Digital-domain calibration of multistep analog-to-digital converters [J ].IEEE JSSC,1992,27(12):1679- 1688.
  • 3Chuang S Y,Sculley T L.A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter [J].IEEE JSSC,2002,37 (6):674- 683.
  • 4MayersMK,ChinSW.A 200 mW,1 M sample/s,16-b pipelined A/D converter with on-chip 32-b mierocontroller [J].IEEE JSSC,1996,31 (12):1862 -1872.
  • 5Lee S H,Song B S.A direct code error calibration technique for two-step flash A/D converters [J].IEEE TCS,1989,36(6):919-922.
  • 6Lee H S.A 12-b 600 KS/s digitally self-calibrated pipeline algorithmic ADC[J].IEEE JSSC,1994,29(4):509-515.
  • 7Lin Y-M,KimB,Gray PR.A 13-b 2.5 MHz selfcalibrated pipeline A/D converter in 3-μm CMOS [J].IEEE JSSC,1991,26(4):628-636.

同被引文献7

  • 1王晶.模拟/数字转换技术及其发展趋势[J].微电子学,2005,35(3):221-225. 被引量:9
  • 2ANDERSEN T N,BRISKEMYR A,TELSTO F.A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 μm digital CMOS Design[C]//Automation and Test in Europe,[S.l.]:IEEE Press,2005.
  • 3YANG H Y,SARPESHKAR R.A time-based energy-efficient analog-to-digital converter[J].IEEE J Solid-State Circuits,2005,40(8):1590-1601.
  • 4KARANICOLAS A N,LEEH S,BACRANIA K L.A 15 b 1msample/s digitally self-calibration pipeline ADC[J].IEEE J SolidState Circuits,1993,28(12):1207-1215.
  • 5MAYES M K,CHIN S W.A 200 mW,1Msample/s,16-b pipelined A/D converter with on-chip 32-b microcont roller[J].IEEE J SolidState Circuits,1996,31(12):1862.
  • 6MOON U K,SONG B S.Background digital calibration techniques for pipelined ADC's[J].IEEE Trans Circuits Syst Ⅱ,1997,44 (2):102.
  • 7SONG B S,TOMPSETT M F,LAKSHMIKUMAR K R.A 12-bit 1-msample/ s capacitor error-averaging pipelined A/D converter[J].IEEE J Solid 2 State Circuits,1988,23(6):1324.

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部