摘要
用硬件描述语言VerilogHDL实现了CPU基本流水线,在寄存器级显示了CPU流水线的内部结构,指令的动态流水执行情况可以通过前仿真形成波形图进行观察.
The basic pipeline of CPU is realized by hardware description language (Verilog HDL).Some data correlation is solved by a directional technique.The control correlation is also considered and settled. The inner structure of CPU pipeline is shown at register level. The dynamic execution of pipeline can be observed by wave drawing, which is generated by the pre-simulator.
出处
《内蒙古大学学报（自然科学版）》
CAS
CSCD
北大核心
2004年第3期325-331,共7页
Journal of Inner Mongolia University：Natural Science Edition
基金
国家自然科学基金60303033
内蒙古自然科学基金资助项目(200308020212)
内蒙古高校科学研究项目(NJ03120)
内蒙古大学博士启动基金资助项目
关键词
流水线
定向技术
数据相关
控制相关
pipeline
directional technique
data correlation
control correlation
