摘要
由小数分频频率合成器中相位累加器与数字一阶调制器的等效性出发,用ADS软件仿真证实了高阶数字调制对量化相位噪声的高通整型功能,从而有效地解决了小数分频的杂散问题.最后硬件电路实现了基于调制的小数分频跳频频率合成器,频率范围为590~1000MHz,在偏离主频10KHz时相噪优于-93.76dBc/Hz,频率分辨率可以小于100Hz,转换时间小于50,在跳频频率间隔1MHz时每秒可达2万跳.
Based on the equivalence of noise-shaping function between the first order delta-sigma modulator and traditional phase accumulator of fractional-N frequency synthesizer, noise characteristics of the high order delta-sigma modulator is analyzed and experimentally verified. With the influence of the high order delta-sigma modulator, the spurious phase noise introduced by fractional-N division possesses of high-pass characteristics can be suppressed by the loop filter of the phase-lock-loop (PLL). A fractional-N frequency synthesizer with the high order delta-sigma modulator is realized using monolithic IC. The working frequency is between 590 to 1000MHz. The measured phase noise is lower than 93.76dBc/Hz at 10KHz offset. Ultra-small step size is 100 Hz or less with switching time less than 50ms, satisfying the requirement of most wireless communication systems.
出处
《电路与系统学报》
CSCD
2004年第1期26-30,共5页
Journal of Circuits and Systems
基金
重庆市/信息产业部移动通信技术重点实验室开放课题基金资助项目
关键词
频率合成器
小数分频
△-∑调制
frequency synthesizer
fractional-N division
delta-sigma modulator (续第25页)(from page 25)
