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一种通用雷达信号处理机的设计 被引量:2

A Design of Universal Radar Signal Processor
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摘要 在基于VME总线或CPCI总线的雷达信号处理机中,板与板之间的数据传输速率受限于总线的速率。针对现有的雷达信号处理机板间的数据传输速率较低的问题,本文提出了一种新的设计方法,即采用DSP和FPGA相结合的设计方法,利用FPGA提供的高速串行收发通道进行板间的数据传输,使板间的数据传输速率获得大幅度的提升,同时也有效地改善了板内DSP间的数据传输问题。 The data transfer rate between varied boards in radar signal processors based on VME or CPCI bus was limited by the bus rate. To solve the problem of the low data transfer rate between varied boards in radar signal processors,this paper proposes a new design method, combining the DSP with FPGA and using the highspeed serial channels built in the FPGA to transfer data between varied boards. Then the data transfer rate between varied boards is improved greatly. Meanwhile,the problem of the data transfer between DSPs in the same board is also solved effectively.
出处 《雷达与对抗》 2003年第4期13-17,共5页 Radar & ECM
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参考文献2

  • 1Stratix GX FPGA Family Data Sheet Altera,2002.
  • 2TMS320C6713--Float-Point Digital Signal Processor[M]. Texas Instruments,2002.

同被引文献3

  • 1[美]John G.Ackenhusen(李玉柏,杨乐,李征等译).Real-Time Signal Processing:Design and Implementation of Signal Processing Systems(实时信号处理-信号处理系统的设计与实现)[M].北京:电子工业出版社,2002年7月.
  • 2The ADSP-TS101S TigerSHARC(r) On-chip SDRAM Controller, Analog Devices, December, 2003.
  • 3Analog Devices Inc. ADSP TS201 Tiger SHARC proce- ssor hardware reference[R]. USA: ADI,2004.

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