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考虑串扰影响的时延测试 被引量：3

Delay Test Pattern Generation Considering Crosstalk-induced Effects
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摘要 超深亚微米工艺下,串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生,大大提高了算法的效率。实验表明,以该算法实现的系统可以在一个可接受的时间内,对一定规模的电路的串扰时延故障进行测试产生。 Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. In this paper, we address the problem of delay testing considering crosstalk-induced delay effects. A delay test pattern generation technique is proposed base on waveform sensitization. Crosstalk-induced effects on critical paths are targeted to improve test effectiveness of delay testing. Therefore, it can be applied to circuits of reasonable sizes by generating delay tests considering crosstalk-induced effects within an acceptable amount of time.
作者 张月 李华伟 宫云战 李晓维
机构地区 中国科学院计算技术研究所
出处 《微电子学与计算机》 CSCD 北大核心 2003年第11期73-76,共4页 Microelectronics & Computer
基金 国家自然科学基金主任基金项目(60242001) 计算技术研究所领域前沿青年基金项目(20016280-18)
关键词 集成电路 设计 集成度 串扰 时延测试 波形敏化 Crosstalk, Delay testing, Waveform sensitization, Critical path
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献9

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同被引文献20

  • 1李真,周德安,徐伯良.低冗余并行总线容错技术[J].微电子学与计算机,1995,12(6):9-13. 被引量：1
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  • 3Weiyu C, Gupta S K, Breuer M A. Test generation in VLSI circuits for crosstalk noise[C]//Proceedings International Test conference. Los Angeles: University of Saithem Califonia, 1998:641 - 650.
  • 4Krstic A, Jing - Jia L, Yi - Min J, et al. Delay testing considering crosstalk- induce effects[ C]//Proceedings International Test Conference. Washington: IEEE Computer Society, 2001:558 - 567.
  • 5Satyendra R. Crosstalk delay analysis in very deep submicron VLSI circuits[ D]. Texas: Southern Mehodist University, 2004.
  • 6Ba Xiaoliang. Modeling and testing for signal integrity in nanometer system- on- chips[ D]. California: University of California, 2003:24 - 28.
  • 7Aniket, Arunachalam R. A nover algorithm for testing crosstalk induce delay faults in VLSI circuits[ C]//IEEE 2005. India, Madras: Irchan Inst of Techvol, 2005:479 - 484.
  • 8Ahmed N, Tehranipour M H, Nourani M. Extending JTAG for Testing Signal Integrity in SoCs[C]// Proc Design, Automation and Test Europe. Washington, DC, USA..IEEE, 2003:218-223.
  • 9TehranipourM H, Ahmed N, NouraniM. Multiple transition model and enhanced boundary scan architecture to test interconnects for signal integrity [C]// Proc 21st IntConf Computer Design. San Jose, CA, USA.. IEEE, 2003:554-559.
  • 10IEEE. IEEE Std 1149. 1-2001 Standard Test Access Port and Boundary-Scan Architecture[s]. New York: IEEE Standard Board, 2001.

引证文献3

二级引证文献4

微电子学与计算机
2003年 第11期

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