摘要
针对直接数字频率合成的相位截尾误差 ,提出了采用高速CPLD设计实时连续正弦运算模块彻底避免相位截尾误差问题 ,给出了几种可行的算法分析和谱纯度仿真讨论。该模块具有较好的输出信号质量 ,运行速度与DDFS相当 ,不仅可以和单片机构成两片结构的信号发生器 ,也可以作为信号源嵌入到各种片上电子系统设计中去 ,具有设计的灵活性和底层可重用性。
This paper puts forward a real-time sine module based on high-speed CPLD to avoid phase-cut-error of DDFS. The analysis of some feasible algorithms and emulations of iutput spectrum are also given in this paper. The output quality of this module is good with a speed corresponding to the speed of DDFS. Not only can this be used to constitute a 2-chip intellectualized sine-signal generator, but also used as a signal source to be embedded into various one-chip systems.
出处
《南通职业大学学报》
2001年第3期27-31,共5页
Journal of Nantong Vocational University
