摘要
本文提出了一种寄存器级与门级和功能级混合的模拟算法及其具体实现,并从对其效率进行的分析中可以着到,该算法使得模拟能够取各家之长,以尽量小的代价获得最大效益.
This paper proposes an algorithm for multi-level logic simulation, which supports top-down hierarchical design verification. It is mixed at three levels of simulation: the register-transfer, functional and gate level, taking features of each level of simulation. Analyzing its effect, we can know that digital designers can verify their circuits more properly and efficiently by using this algorithm.
出处
《计算机研究与发展》
EI
CSCD
北大核心
1989年第10期51-55,共5页
Journal of Computer Research and Development
