摘要
基于CMOS传输门,分析了单、双沿触发器的逻辑结构,分析了一种晶体管数较少的CMOS双沿触发器,并用PSPICE程序进行了模拟,结果表明这种双沿触发器具有完整的逻辑功能,且具有结构简单、延迟时间短和数据处理能力高的优点,另外,与传统的单沿触发器相比,其功耗大约减少了61%。
In this paper,the logic constructions of a double-edge-triggered flip-flop and a single-edge-triggered flip-flop are analyzed on the basis of CMOS transmission gate.We introduce a set ofnovel double-edge-triggered flip-flop which can be implemented with fewer transistors than anyprevious design. Simulation using SPICE shows that this DET-FF has ideal logic functionality, asimpler structure,lower delay time and higher maximum data rate .The power dissipation in the DET-FF and traditional SET-FF is compared via consideration and simulations and it is shown that theproposed DET-FF reduces power dissipation by 61 while keep the same date rate.
出处
《半导体技术》
CAS
CSCD
北大核心
2003年第4期65-67,75,共4页
Semiconductor Technology
关键词
数据选择器
传输门
CMOS
双沿触发器
single-edge-triggered flip-flop
double-edge-triggered flip-flop
multiplexer
trans-mission gate
