摘要
利用在系统可编程逻辑器件ispLSI6192芯片构造 4个双向并独立的 12 8× 9位FIFO高速数据存储栈区 (FIFO) ,并利用芯片内部快速进位逻辑建立快速地址寄存器和地址自动加 1计数器 ,同时利用该芯片的门阵列建立FIFO控制逻辑 ,控制逻辑分别对 4个FIFO栈区进行读写管理控制 ;即将系统的高速数据栈区及其控制逻辑功能做在同一个芯片上 ,从而提高计算机数据管理通信的速度、效率 。
Applying ispLSI6192 device making four bi directional high speed data memory(FIFO)of 128×9 bit, making address counter and address register base on high speed adding logic of the device and making controlling logic base on programmable gate array and programmable register array,controlling logic can manage and control reading or writing operation of FIFO1～4 data memory; that is making system's high speed data memory and it's controlling logic in same device, so we can improve efficiency and speed of computer data managing and communications and improve system's integer and reduce system's error.
出处
《控制工程》
CSCD
2003年第1期69-71,共3页
Control Engineering of China
