摘要
知识产权(IP)核具有便捷性、通用性等特点,广泛应用于集成电路(IC)和可编程逻辑阵列(FPGA)设计。文章提出一种支持多主设备片内总线IP核的设计与实现。所提出的IP核支持多主设备,承载共享地址多路数据(SAMD)拓扑结构、可编程数据宽度、总线仲裁器、存储器和输入/输出(I/O)访问、三态数据接口等。所提出的方案已经通过设计、仿真,成功应用于多型产品。
Intellectual property(IP)core has the characteristics of convenience and generality,and is widely used in integrared circuit(IC)and field programmable gate array(FPGA)design.This article proposes design and implementation of supporting muti-master onchip-bus IP core.The proposed IP core supports muti-master,and carries shared address multiple data(SAMD),programmable data wide,bus arbiter,memory and input/output(I/O)access,tri-state data interface.The proposed scheme is successfully used in many products with design and simulation.
作者
徐雄斌
劳羡波
徐轶言
XU Xiongbin;LAO Xianbo;XU Yiyan(Computing Environment Department,Wuhan Digital Engineering Institute,Wuhan 430070,China)
出处
《微型电脑应用》
2026年第1期307-310,316,共5页
Microcomputer Applications
