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An ultra-low power wake-Up timer compatible with n-FET based flexible technologies

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摘要 Flexible integrated circuits(FlexICs)have drawn increasing attention,particularly in remote sensors and wearables operating in a limited power budget.Here,we present an ultra-low power timer designed to wake-up an external circuit periodically,from a deep-sleep state into an active state,thereby largely reducing the system power consumption.We achieved this with a circuit topology that exploits the transistor’s leakage current to generate a low frequency wake-up signal.This topology is compatible with IC technologies where only n-type transistors are available.The design was implemented with the sustainable FlexIC process of PragmatIC,that is based on Indium Gallium Zinc Oxide(IGZO)thin-film transistors.Our timer generates mean wake-up frequency of 0.24±0.15 Hz,with a mean power consumption of 26.7±14.1 nW.In this paper,we provide details of the Wake-Up timer’s design and performance at different supply voltages,under temperature variations and different light conditions.
出处 《npj Flexible Electronics》 2025年第1期1885-1897,共13页 npj-柔性电子(英文)
基金 supported by the European Union’s Horizon 2020 Research and Innovation Programme,under grant agreement Nr.951774 support through the FPU fellowship grant(FPU22/01008) the sponsorship of the Alexander von Humboldt Professorship of the Humboldt Foundation and the Federal Ministry for Education and Research(Germany) the European Community’s Horizon Europe program(ERC-POC FLETRAD,grant agreement no.101082283) from National Funds through the FCT-Fundação para a Ciência e a Tecnologia,I.P.,projects LA/P/0037/2020,UIDP/50025/2020 and UIDB/50025/2020 supported by the Generalitat de Catalunya through the grant 2021 SGR 01108.
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