摘要
为保证电流等级满足日益增长的需求,使用碳化硅(SiC)芯片的功率模块需要并联的芯片数量较大,然而芯片数量增多会使得功率模块可靠性降低,因此需要关注功率模块中并联芯片的具体布局。本文首先建立起功率模块中关于并联芯片的互热阻函数,在此基础上利用快速非支配排序遗传算法(NSGA-Ⅱ)求解得到并联芯片对应的优化模型布局,并在相同条件下分别制作了优化模型布局模块与原布局模块。接着对不同布局的模块进行双脉冲测试,将得到的功耗代入有限元仿真分析仿真结温。最后通过Buck实验利用红外热像仪获取了不同布局下芯片的结温,通过验证,该优化模型布局相较于原布局的并联芯片结温更均衡。
In order to ensure that the current level meet the growing demand,the power module using silicon carbide(SiC)chip needs a large number of chips in parallel.However,the increase in the number of chips will reduce the reli⁃ability of the power module,so it is necessary to pay attention to the specific layout of the parallel chips in the power module.The mutual thermal resistance function of the parallel chips in the power module is established.On this basis,the fast non-dominated sorting genetic algorithm(NSGA-Ⅱ)is used to solve the optimization model layout corresponding to the parallel chips,and the optimization model layout module and the original layout module are made under the same conditions.Then the double pulse test is carried out on the modules with different layouts,and the obtained power consumption is substituted into the finite element simulation to analyze the simulation junction temperature.Finally,the junction temperature of the chip under different layouts is obtained by Buck experiment using an infrared thermal imager.Through verification,the optimized model layout is more balanced than the parallel chip junction temperature of the original layout.
作者
罗茜
王一庆
宋雨佳
孙鹏
赵志斌
Luo Qian;Wang Yiqing;Song Yujia;Sun Peng;Zhao Zhibin(State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources,North China Electric Power University,Beijing 102206,China)
出处
《电力电子技术》
2025年第12期129-136,共8页
Power Electronics
基金
省部共建电工装备可靠性与智能化国家重点实验室(河北工业大学)开放课题基金(EERI_KF2022003)。
关键词
功率模块
并联芯片
结温均衡
power module
parallel chips
junction temperature balance
