摘要
祖冲之(ZUC)算法是我国自主研发的商用序列密码算法,已被应用于服务器实时运算和大数据处理等复杂需求场景,ZUC的高速实现对于其应用推广具有重要的实用意义。基于此,针对ZUC适用环境的FPGA实现高性能要求,通过优化模乘、模加等核心运算,并采用流水化结构设计,在FPGA硬件平台上实现了ZUC算法。实验结果表明,ZUC算法核的数据吞吐量可达10.4 Gb/s,与现有研究成果相比,降低了关键路径的延迟,提升了算法工作频率,在吞吐量和硬件资源消耗方面实现了良好的平衡,为ZUC算法的高性能实现提供了新的解决方案。
The ZUC algorithm is a commercial sequence cipher algorithm independently developed in China,which has been applied in complex scenarios such as real-time server computation and big data processing.The high-speed implementation of ZUC has important practical significance for its application promotion.Based on this,the ZUC algorithm was implemented on the FPGA hardware platform to meet the high-performance requirements of the ZUC applicable environment.By optimizing core operations such as modular multiplication and modular addition,and adopting a streamlined structure design,the ZUC algorithm was realized.The experimental results show that the data throughput of the ZUC algorithm core can reach 10.4 Gb/s.Compared with existing research results,it reduces the delay of critical paths,improves the operating frequency of the algorithm,and achieves a good balance between throughput and hardware resource consumption,providing a new solution for the high-performance implementation of the ZUC algorithm.
作者
卫志刚
李鑫
高园
Wei Zhigang;Li Xin;Gao Yuan(XinDaJieAn Mobile Information Security Key Technology National Joint Local Engineering Laboratory,Zhengzhou 450004,China;School of Mathematics and Statistics,Zhengzhou University,Zhengzhou 450001,China)
出处
《电子技术应用》
2025年第10期69-73,共5页
Application of Electronic Technique
基金
河南省重大科技专项(181200211200)。
