摘要
采用0.18μm BCD工艺,实现了一款可兼容双通道/半桥架构的隔离栅极驱动器。其输入、驱动侧电源电压分别为3V~18 V、4.5V~35 V,每通道最大拉/灌(source/sink)电流为6/8 A,隔离电压5.7 kVrms,CMTI 150 kV/μs。设计了一种兼容双通道、半桥架构驱动模式控制电路,通过一个兼容高压的芯片引脚DT,可灵活配置双通道直通输出模式、半桥最小死区时间模式及半桥可编程死区时间模式。仿真与测试结果表明:芯片兼容双通道/半桥驱动模式,DT引脚接入高压时芯片可靠工作;基于片外电阻实现的死区时间在10 ns~2μs范围线性可调;外接电阻分别为10 kΩ和46 kΩ时,两通道间的死区时间测试值分别为105 ns、103 ns和468 ns、457 ns,与理论设计值误差分别为5%、3%和1.7%、0.65%。
Based on 0.18μm BCD process,a dual-channel/half-bridge compatible isolated gate driver is designed,which has 3V to 18 V input-side voltage,4.5V to 35 V driver-side voltage,6/8 A maximum source/sink current per-channe,5.7 kVrms isolation voltage and CMTI 150 kV/μs.A drive-mode control circuit compatible with dual-channel and half-bridge topology is designed.Through a high-voltage-tolerant pin DT,dual-channel direct-output mode,half-bridge minimum dead time mode and half-bridge programmable dead time mode can be flexibly configured.Simulation and measurement results show that dual-channel/half-bridge compatibility,the DT pin withstands high voltage reliably,and the dead time,set by an external resistor,is dynamically adjustable from 10 ns to 2µs.With external resistors of 10 kΩand 46 kΩ,the measured dead times are 105 ns,103 ns and 468 ns,457 ns respectively,deviating only 5%,3%,and 1.7%,0.65%from the design values.
作者
黎荣佳
马春宇
张龙
张峰
LI Rongjia;MA Chunyu;ZHANG Long;ZHANG Feng(Analog Circuit Development Center,Beijing GL-Microelectronics Technology Co.,Ltd.,Beijing 100190,China)
出处
《微电子学与计算机》
2025年第10期178-186,共9页
Microelectronics & Computer
