摘要
随着FPGA设计复杂性的增加,单元的高度密集性和布线资源的有限性容易导致布线拥塞,在物理设计的早期阶段对布线拥塞进行预测并实施相关策略可以有效缩短设计周期并降低成本。基于复杂网络特征保留电路拓扑性质的特性,提出一种利用复杂网络和Patched EDM的FPGA布线拥塞预测方法。在布局阶段提取与布线拥塞相关的电路特征和复杂网络特征,根据特征重要性映射成RGB图像,并在EDM中引入Patch转换来捕捉图像中与布线拥塞相关的关键信息。实验结果表明,本方法 SSIM的平均值为85.01%,PSNR为27.854 7 dB,NRMS为12.91%,PIX为18.73%,相对于现有最先进的模型表现出更好的预测效果,证明了提出的Patched EDM在预测布线拥塞方面的有效性。
As the design complexity of field programmable gate arrays(FPGAs)increases,the high density of internal units and limited routing resources can result in routing congestion.Predicting the routing congestion in the early stage of physical design and implementing strategies can effectively reduce design time and costs.This paper proposes a model for predicting FPGA routing congestion using complex networks and patched EDM(Elucidating the Design Space of Diffusion-Based Generative Model),leveraging the circuit topology characteristics preserved by complex network features.During the placement stage,circuit features and complex network features related to routing congestion are extracted and mapped into RGB images based on feature importance.Subsequently,Patch transformation is introduced to capture key congestion-related information.Experimental results show that the method achieves an average SSIM of 85.01%,PSNR of 27.8547 dB,NRMS of 12.91%,PIX and of 18.73%,outperforming the recent state-of-the-art models.
作者
聂廷远
刘鹏飞
郭达
杜洋
NIE Tingyuan;LIU Pengfei;GUO Da;DU Yang(College of Information and Control Engineering,Qingdao University of Technology,Qingdao,Shandong 266520,P.R.China)
出处
《微电子学》
北大核心
2025年第4期627-634,共8页
Microelectronics
基金
国家自然科学基金资助项目(61572269)
山东省自然科学基金资助项目(ZR2021MF101)。
关键词
现场可编程门阵列
布线拥塞
复杂网络
机器学习
扩散模型
field programmable gate array
routing congestion
complex network
machine learning
diffusion model
