摘要
针对高速串行接口(SerDes)中非归零码信号在长距离传输和严重信道衰减下误码率高的问题,发送端常采用前向反馈均衡技术进行处理。文章基于UMC 28 nm CMOS工艺,设计一种采用8 bit数模转换器架构的并行可配置FFE高速SerDes发送端。并行输入信号与已存储的8个10 bit抽头系数通过可配置FFE中乘法器模块和并行进位加法器模块进行逻辑运算,实现信号预均衡处理,并通过与非门、共源共栅器件以及复位路径组成的高速4∶1多路复用器终端输出网络采用源串联端接结构实现更低的功率损耗。仿真结果表明:该发送端在1.05 V电压供电以及信道衰减为18.59 dB@20 GHz的条件下,输出40 Gb/s NRZ信号的眼高为378.4 mV,眼宽为18.53 ps(0.74 UI),整体版图面积为0.055 mm^(2),整体电路功耗为41.8 mW。
Owing to long transmission distances and high bit-error rates caused by serious channel attenuation,non-return-to-zero(NRZ)code signals are usually processed using forward feedback equalization(FFE)at high-speed serial interface(SerDes)transmitters.In this study,based on the UMC 28 nm CMOS process,a parallel-configurable FFE high-speed SerDes transmitter was designed using an 8-bit digital-to-analog converter architecture.The parallel input signal and stored 810-bit tap coefficients are logically operated by the multiplier module and parallel carry adder module in the configurable FFE to realize signal pre-equalization processing.A high-speed 4∶1 multiplexer composed of an AND-NOT gate,a cascode device,and a reset path was adopted.The terminal output network adopted a source series termination structure to reduce power loss.The simulation results showed that when the transmitter was powered by 1.05 V voltage and the channel attenuation was 18.59 dB@20 GHz,the eye height of the output 40 Gb/s NRZ signal was 378.4 mV,eye width was 18.53 ps(0.74 UI),overall layout area was 0.055 mm2,overall circuit power consumption was 0.055 mm^(2),and power consumption of the complete circuit was 41.8 mW.
作者
任一凡
张春茗
陶保明
REN Yifan;ZHANG Chunming;TAO Baoming(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,CHN)
出处
《半导体光电》
北大核心
2025年第4期673-679,共7页
Semiconductor Optoelectronics
基金
国家重点研发计划项目(2019YFB1803600)。
关键词
并行可配置前向反馈均衡技术
源串联端接
数模转换器
4∶1多路复用器
parallel configurable feed-forward equalization technology
source series-terminated driver
digital-to-analog converter
4∶1 multiplexer
