摘要
为了有效降低并网逆变器数字延时,设计了基于现场可编程门阵列(FPGA)的超低数字延时并网逆变器实验平台。该平台采用紫光同创公司的PGL25G系列FPGA作为驱动控制芯片,德州仪器公司的DSP28337D作为算法控制芯片,并运用即时采样方法实现了基于FPGA的超低数字延时空间矢量脉冲宽度调制(SVPWM)数字化。与传统的对称规则采样方法相比,该方法显著降低了系统的计算延时,从而有效降低了系统并网电流谐波含量,提升了系统稳定性。
To effectively reduce the grid-connected inverter’s digital delay,an ultra-low digital-delay grid-connected inverter experimental platform based on field-programmable gate array(FPGA)was developed.This platform utilizes the PGL25G series FPGA chip from Pango Micro and the DSP28337D control chip from Texas Instruments.By adopting a real-time sampling method,it achieves FPGA^(-)based ultra-low digital-delay space vector pulse width modulation(SVPWM)digitization.Compared with traditional symmetrical regular sampling methods,this approach significantly reduces computational delays in the system,thereby lowering the harmonic content of the grid-connected current and improving system stability.
作者
张智雄
彭卓彬
谷建伟
ZHANG Zhixiong;PENG Zuobin;GU Jianwei(School of Artificial Intelligence and Automation,Huazhong University of Science and Technology,Wuhan 430074,China)
出处
《实验室研究与探索》
北大核心
2025年第8期84-88,共5页
Research and Exploration In Laboratory
关键词
并网逆变器
现场可编程门阵列
超低数字延时
实验平台
grid-connected inverter
field-programmable gate array(FPGA)
ultra-low digital delay
experimental platform
