摘要
本文设计了一种针对RISC-V架构特性的寄存器分配方法。该方法基于寄存器分配与指令调度优化间的信息交互,结合历史分配策略来调整寄存器分配的结果,旨在减少寄存器分配后的指令依赖,从而更利于后续的指令调度优化,减少指令延迟,提高指令的执行效率。在RISC-V架构下,由于指令集精简,所有计算操作都依赖于寄存器,因此寄存器分配对性能影响显著,合理的分配策略则能充分利用硬件优势。本文方法的核心在于建立了寄存器分配优化与指令调度优化的反馈编译框架,并且通过全局的分配记录指导寄存器分配,实现更具适应性的寄存器分配优化。本方法不仅优化了寄存器分配,减少了对内存访问的需求,还提高了指令执行的连续性。本文基于RISC-V架构对SPECCPU2006基准测试集进行了测试,在整数基准程序上取得了平均1.4%的性能提升,相比于传统LLVM寄存器分配方法有明显改进。本文方法不仅有效提升了寄存器利用效率,还进一步验证了寄存器全局优化策略在提升RISC-V架构性能方面的潜力,为未来RISC-V编译器优化提供了有益的参考。
This paper designs a register allocation method tailored to the characteristics of the RISC-V architecture.The method is based on the information interaction between register allocation and instruction scheduling optimization,combined with historical allocation strategies to adjust the register allocation results.The aim is to reduce instruction dependencies after register allocation,thereby facilitating subsequent instruction scheduling optimization,reducing instruction latency,and improving execution efficiency.In the RISC-V architecture,due to the simplified instruction set,all computational operations depend on registers,register allocation has a significant impact on performance.A reasonable allocation strategy can fully leverage hardware advantages.The core of the method in this paper is the establishment of a feedback compilation framework between register allocation optimization and instruction scheduling optimization.By guiding register allocation through global allocation records,the method achieves more adaptable register allocation optimization.This approach not only optimizes register allocation and reduces memory access requirements,but also improves instruction execution continuity.Based on the RISC-V architecture,the SPECCPU2006 benchmark suite is tested,achieving an average 1.4%performance improvement on integer benchmark programs,demonstrating significant improvement over the traditional LLVM register allocation method.This method effectively improves register utilization,and further validates the potential of global register optimization strategies in enhancing the performance of the RISC-V architecture,providing valuable reference for future RISC-V compiler optimizations.
作者
朱珂
何先波
滕芊芊
ZHU Ke;HE Xianbo;TENG Qianqian(School of Electronic and Information Engineering,China West Normal University,Nanchong 637009,Sichuan,China)
出处
《智能计算机与应用》
2025年第5期61-67,共7页
Intelligent Computer and Applications
关键词
寄存器分配
编译器
指令调度
线性扫描算法
register allocation
compiler
instruction scheduling
linear scan algorithm
