摘要
为了解决国外芯片供应的不稳定性以及满足设计自主可控的要求,在国产FPGA上采用硬件方式实现基于以太网的UDP通信协议,利用SystemVerilog语言设计了一种UDP协议栈IP核.该IP核支持主动ARP请求、被动ARP应答、ARP表查询、ICMP协议、IP协议、UDP协议以及协议间的仲裁控制;同时支持AMD公司的三速以太网IP核,可以直接与三速以太网IP核适配.该协议栈IP核只采用常用的FIFO IP,其余均以源码形式设计,便于在其他国产FPGA上进行移植部署.最后将设计完成的IP核放在国微SMQ7K325TFFG900芯片上进行了测试.测试结果表明,该IP核可以实现UDP协议通信,性能良好.
In order to solve the instability problem of foreign chip supply and meet the requirements of self-reliant and controllable design,the Ethernet-based UDP communication protocol is implemented in hardware mode on domestic FPGA,and SystemVerilog language is used to design a UDP protocol stack IP core.The IP core supports active ARP request,passive ARP response,ARP table query,ICMP protocol,IP protocol,UDP protocol,and inter-protocol arbitration control,and at the same time,it also supports AMD’s triple-speed Ethernet IP core,able to be directly adapted to the triple-speed Ethernet IP core.The protocol stack IP core only adopts the commonly used FIFO IP,and the rest are designed in the form of source code,which is easy to be transplanted and deployed on other domestic FPGAs.Finally,the designed IP core is tested on on SSMEC SMQ7K325TFFG900 chip.The test results show that the IP core can realize UDP protocol communication,with good performance.
作者
李森
唐建
袁强
LI Sen;TANG Jian;YUAN Qiang(Automation Research Institute Co.,Ltd.,China South Industries Group,Mianyang 621000,China)
出处
《空天预警研究学报》
CSCD
2024年第5期347-352,363,共7页
JOURNAL OF AIR & SPACE EARLY WARNING RESEARCH
