摘要
为了降低无线传感器网络(WSNs)成本,设计了一种低面积部分并行8级流水的低密度奇偶校验(LDPC)码译码器。针对最小和(MS)算法校验节点信息值计算复杂度高而导致硬件资源消耗过多的问题,提出一种新的计算校验节点信息值的算法。该算法只需计算变量节点传递到校验节点信息的绝对值最小值。与MS算法相比,降低计算复杂度66.6%。现场可编程门阵列(FPGA)综合结果表明:校验节点面积减少43%,路由面积减少30%,变量节点面积减少21%。在使用55 nm CMOS工艺下,译码器时钟频率600 MHz,信噪比4.4 dB条件下,数据吞吐率29 Gbps,面积1.7 mm^(2)。
In order to reduce cost of wireless sensor networks(WSNs),a low area partially parallel 8-stage pipelined low density parity check(LDPC)code decoder is designed.In order to solve the problem of excessive hardware resource consumption caused by high computational complexity of the check node information value in Min-Sum(MS)algorithm, a new algorithm for calculating the check node information value is proposed.The algorithm only needs to calculate the minimum absolute value of the information from the variable node to the verification node.Compared with the MS algorithm, the computational complexity is reduced by 66.6 %.Field programmable gate array(FPGA)synthesis results show that the verification node area is reduced by 43 %,the routing area is reduced by 30 %,and the variable node area is reduced by 21 %.With 55 nm CMOS technology, the decoder clock frequency is 600 MHz, the signal-to-noise ratio is 4.4 dB,the data throughput is 29 Gbps, and the area is 1.7 mm^(2).
作者
吴冰瑞
陆玲霞
WU Bingrui;LU Lingxia(School of Micro-Nanoelectronics,Zhejiang University,Hangzhou 310058,China;School of Electrical Engineering,Zhejiang University,Hangzhou 310058,China)
出处
《传感器与微系统》
CSCD
北大核心
2022年第11期77-80,共4页
Transducer and Microsystem Technologies
关键词
无线传感器网络
低密度奇偶校验码
最小和算法
置信传播
wireless sensor networks(WSNs)
low density parity check(LDPC)code
Min-Sum(MS)algorithm
belief propagation
