摘要
为解决远距离高速信号传输的数据校验问题,提高编译码算法的数据传输效率与纠错效率,设计了一种基于伽罗华域LDPC的时分复用系统.采用模块化思想和流水线思想设计电路架构,并在LDPC译码部分采用了增强型硬判决算法,使LDPC编解码模块的码率达到了0.8125,在FPGA平台上达到了400MHz的工作频率,时分复用系统单次传输10240bit数据时最快可达43.8μs.与其他文献成果相比,本系统在FPGA上实现较高的时钟频率,同时具有较高的码率和吞吐率,针对不同的数据位宽具有一定的通用性,可应用于长距离高速信号传输场合.
In order to solve the data verification problem for long-distance high-speed signal transmission and improve the data transmission and error correction efficiencies of encoding and decoding algorithms,a time division multiplexing system based on Galois domain LDPC was designed.The circuit architecture was designed from the perspective of modularization and pipeline.The enhanced response decision algorithm was adopted in the LDPC decoding part to make the bit rate of LDPC codec module reach 0.8125 and the working frequency get 400MHz on the FPGA platform.The fastest single-time transmission of 10240 bit data with this time division multiplexing system reaches 43.8μs.Compared with other literature reports,this system supports higher clock frequency for FPGA implementation,and has relatively higher code and throughput rates.It has certain universality with regard to different data bit widths,and can be applied to long-distance high-speed signal transmission.
作者
任建
于皓哲
辛晓宁
刘思源
REN Jian;YU Hao-zhe;XIN Xiao-ning;LIU Si-yuan(School of Information Science and Engineering,Shenyang University of Technology,Shenyang 110870,China)
出处
《沈阳工业大学学报》
CAS
北大核心
2022年第1期62-67,共6页
Journal of Shenyang University of Technology
基金
国家自然科学基金面上项目(6187011861)
辽宁省教育厅青年育苗项目(LQGD2020009).
关键词
时分复用
伽罗华域
低密度奇偶校验码
吞吐率
现场可编程门阵列
传输效率
码率
time division multiplexing
Galois domain
low density parity check code(LDPC)
throughput
field programmable gate array(FPGA)
transmission efficiency
code rate
