摘要
不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.
Unlike the previous methods of realizing reversible finite state machine(FSM)by reconstructing FSM behavior,a circuit structure for reversible FSM realization is proposed in this paper.The circuit structure mainly includes two parts,one for next state and output calculation,the other for state preset,data sampling and storage.In the proposed reversible FSM,there is no complete reversible flip-flops such as JK,D and T,but their functions can be realized by the proposed reversible FSM.Furthermore,a synthesis method of reversible sequential circuits based on the proposed reversible FSM is presented and verified by an example.Compared with the synthesis methods of reversible finite state machine based on behavior reconstruction,the proposed synthesis method in this paper can avoid the solution of the inverse state machine of the original state machine and adding extra bits,which makes the synthesis process simpler.
作者
吴钰
张莹
王伦耀
储著飞
夏银水
WU Yu;ZHANG Ying;WANG Lun-yao;CHU Zhu-fei;XIA Yin-shui(Faculty of Electrical Engineering and Computer Science,Ningbo University,Zhejiang,Ningbo 315211,China)
出处
《电子学报》
EI
CAS
CSCD
北大核心
2020年第11期2226-2232,共7页
Acta Electronica Sinica
基金
国家自然科学基金(No.61471211,No.U1709218,No.61871242)
浙江省自然科学基金(No.LY19F040004)
宁波市自然科学基金(No.2019A610077)。
关键词
可逆逻辑
有限状态机
时序电路
逻辑综合
reversible logic
finite state machine
sequential circuits
logic synthesis
