摘要
根据JESD204B协议,设计了一种应用于8 Gsps 12 bit模数转换器(analog-to-digital,ADC)接口电路中的8B10B编码器。该编码器采用双字节并行实现方案将系统时钟由500 MHz降低至250 MHz,通过添加1 bit均衡指示位,使得极性信息先于编码结果产生,减少了极性计算与传递引起的延迟;使用负极性编码,减小对查找表资源的使用。实验结果表明,该编码器能够支持12.9 Gbps的最大通道传输速率,相比级联型编码器和单字节编码器数据传输速率更高。所设计的编码器能够满足8 Gsps 12 bit模数转换器的应用需求。
According to JESD204B protocol,an 8B10B encoder is designed for 8 Gsps 12 bit analog-to-digital(ADC)interface circuit.The encoder uses a dual-byte parallel implementation scheme to reduce the system clock from 500 MHz to 250 MHz.By adding 1 bit equalization indicator bit,the polarity information is generated prior to the coding result,which reduces the delay caused by polarity calculation and transmission,and uses negative polarity coding to reduce the use of lookup table resources.The experimental results show that the encoder can support the maximum channel transmission rate of 12.9 Gbps,and the data transmission rate is higher than that of cascade encoder and single byte encoder.The coder designed can meet the application requirements of 8 Gsps 12bit ADC.
作者
张博
陶晓旭
刘宇
ZHANG Bo;TAO Xiaoxu;LIU Yu(School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China)
出处
《西安邮电大学学报》
2019年第5期47-52,共6页
Journal of Xi’an University of Posts and Telecommunications
基金
陕西省技术创新引导专项基金资助项目(2017ZKC02-56)
西安市集成电路重大专项项目(201809174CY3JC)
