摘要
针对现有基于传统布尔逻辑进行逻辑级功耗优化的局限性,提出逻辑函数基于传统布尔逻辑和Reed-Muller逻辑的双逻辑门级图形表示的功耗优化方法.首先在逻辑级采用简化有序二叉决策图实现逻辑函数的双逻辑表示;然后通过代数分解和布尔分解获得双逻辑门级表示,进而基于功耗成本估算进行门级功耗优化;最后实现变量级和门级的两层次的优化方法.与学术界著名的ABC和工业界最先进的工具Design Compile(DC)进行比较的实验结果表明,该方法均具有一定的优势.
To cope with the limitation of traditional Boolean logic based power optimization at logic level,power optimization method of logic function based on traditional Boolean (TB) logic and Reed-Muller (RM)logic called dual logic is proposed with gate level diagram expression. First, logic function is represented in TB logic and RM logic. Then gate level expression is obtained through iterative algebraic and Boolean decomposition.Further, gate-level power optimization is carried out under the guidance of the power cost. Finally,a two level power optimization method at variable level and gate level is implemented. Experimental results show that the proposed method is more efficient than the state-of-art academic and commercial synthesis tools.
作者
马雪娇
厉琼莹
张骏立
夏银水
Ma Xuejiao;Li Qiongying;Zhang Junli;Xia Yinshui(Institute of Circuits and System, Ningbo University, Ningbo 315211)
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2017年第3期509-518,共10页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金重点项目(61131001)
