期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits 被引量：5

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits
原文传递
导出
摘要 An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones. An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.
作者 陈偕雄 ClaudioMoraga
机构地区 DepartmentofElectronicEngineering DepartmentofComputerScience
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 1995年第6期564-568,共5页 计算机科学技术学报（英文版）
关键词 Multiple-valued logic logic design current mode CMOS circuits Multiple-valued logic, logic design, current mode CMOS circuits
分类号 TP331.13 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献3

  • 1陈偕雄，Proc 23rd International Symposium on Multi-Valued Logic，1993年
  • 2Chang Y H，Proc of the 21st International Symposium on Multi-Valued Logic，1991年
  • 3Lei K，Proc of the 21st International Symposium on Multi-Valued Logic，1991年

同被引文献17

  • 1吴训威,邓小卫,应时彦.基于开关信号理论的三值电流型CMOS电路设计[J].电子科学学刊,1993,15(2):113-120. 被引量：15
  • 2THOIDIS I, SOUDRIS D, KARAFYLLIDIS I, et al.Quaternary voltage-mode CMOS circuits for multiple-valued logic [J]. IEE Proceedings-Circuits Devices and Systems, 1998, 145(2):71-77.
  • 3GUO Y B, CURRENT K W. Voltage comparator circuits for multiple-valued CMOS logic [A]. Proceedings of IEEE International Symposium on MultipleValued Logic[C]. Los Alamitos, CA: IEEE Computer Society, 2002. 67-73.
  • 4CURRENT K W. Current-mode CMOS multiple-valued logic circuits [J]. IEEE Journal of Solid State Circuits, 1994, 29(2): 95-107.
  • 5ABD-EL-BARR M, AL-MUTAWA A. A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using currentmode CMOS circuits[A]. Proceedings of IEEE International Symposium on Multiple-valued Logic[C].Los Alamitos, CA: IEEE Computer Society, 2001.15-20.
  • 6HANYU T, KAMEYAMA M. A 200MHz pipelined multiplier using 1. 5V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic[J]. IEEE Journal of Solid State Circuits, 1995,30 (11 ): 1239- 1245.
  • 7HANG G, WU X. Current-mode CMOS circuits design based on current threshold-controllable technique[A]. Proceedings of IEEE Asia Pacific Conference on Circuits and Systems [C]. Piscataway, NJ:IEEE Service Center, 2000. 529-532.
  • 8HANG G, WU X. Current threshold-controllable technique and ternary current-mode CMOS Schmitt circuits[J]. An International Journal: Multiple-Valued Logic, 2001, 7(3-4): 283-294.
  • 9WU X, PROSSER F. CMOS ternary logic circuits [J]. IEE Proceedings, 1990, 137-G (1): 21-27.
  • 10吴训威,陈偕雄,FRANKLINP.PPROSSER.QUATERNARY CMOS CIRCUITS BASED ON TRANSMISSION FUNCTION THEORY[J].Science China Mathematics,1989,32(11):1379-1389. 被引量：1

引证文献5

二级引证文献8

Journal of Computer Science & Technology
1995年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部