摘要
The ARGO-YBJ experiment is presently under construction at the Yangbaijing high Altitude Comsmic Ray Laboratory(4300m a.s.l).90 Km North to Lhasa(Tibet,peolpl's Republic of China) ARGO-YBJ will study fundamental issues in cosmic ray and astroparticle physics by detecting small size air showers.The detector covers-71×74 square meters with a single layer of resistive Plate Counters(RPCs),surrounded by a guard ring partially instrumented.An event-driven data collection scheme is implemented by using a custom bus protocol./Key features of this architecture are block-oriented data transfer and read-out cycles labeled by trigger number,Hardware engines in both master and DAQ boards handle bus transactions and provide event builing capability,achieving real-time data processing with no software overhead.In this paper we present the hardware design of the ARGO experiment's DAQ which benefits from the flexible architecture of in-system reconfigurable FPGAs.The dataacquistition boards specifically developed for this application will be described.
