摘要
根据ARM处理器高性能总线(Advanced High performance Bus)接口协议,设计了可综合32位/16位存储器以及I/O接口RTL代码,替代Cortex-M0试用版(cortex_m0_designstart)中的行为级存储器接口代码.能够在FPGA上构建一个具有存储器架构及I/O读取功能的完整嵌入式系统,满足对Cortex-M0进行系统级快速功能验证的需求.给出了存储器接口及I/O设计方法和代码,并在Altera公司的EP3C40器件上进行了验证,硬件资源为逻辑单元7 688个,存储单元17 408bit.
According to the advanced high performance bus （AHP） interface protocol, the synthesizable RTL code of the 32/16 bit memory and I/O interface is designed. The RTL code replaces the behavior-level memory interface code of in cortex_m0_designstart. The method can build a complete embedded system in FPGA which has the function of memory and I/O architecture to meet the demand for rapid system level function verification using Cortex-M0 IP. The design method is provided in this paper, and the RTL code is verified on Altera＇s EP3CA0 also. The designed hardware system occupies about 7688 logical unit and 17408bits memory cell.
出处
《微电子学与计算机》
CSCD
北大核心
2018年第3期135-139,共5页
Microelectronics & Computer
关键词
CORTEX-M0软核
FPGA
状态机
存贮接口
CORTEX-M0 soft core
field programmable gate arrays
state machines
memory interface
